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jeremylbt
Joined: 22 Aug 2008
Posts: 11
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 22 Aug 2008 6:54 Please advise on the following RAM design!!! |
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Referring to the attached block diagram design:
Are we able to achieve the following steps in 1 clock cycle?
Data from the single port RAM and the dual port RAM is read out, added and write the result back to the single port RAM all in 1 clock cycle. Is this possible?
I've simulated the design and from the timing simulation it seems feasible. Am I wrong in any way?
Please advise. Thanks.
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kvingle
Joined: 05 Nov 2007
Posts: 133
Helped: 12
Location: Mumbai, India.
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| 22 Aug 2008 11:17 Re: Please advise on the following RAM design!!! |
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you are simultaneously writing \ reading from single port RAM is it a typo ?
i think you have interchanged the label of RAMs in pic.
I don't think you can achieve it in single clock.
because data from RAM will come on output port after clock to out delay...and after that you wont be able to save the same data in ram till next clk edge...
normal simulation will not show such difference since it does not consider various inherent delays of real hardware..
try post and route simulation.
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jeremylbt
Joined: 22 Aug 2008
Posts: 11
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| 25 Aug 2008 5:24 Re: Please advise on the following RAM design!!! |
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Thanks for your reply. The figures are laballed as intended. Maybe I shouldn't put Rd/Wr Addr in the single port ram. Should have put only "Addr".
Anyway I've run the timing simulation after post-and-route and the simulation results show that I can read, add and write to the same address in 1 clock cycle. I don't understand why as well.
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