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richardwli
Joined: 24 Jun 2008
Posts: 3
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 21 Aug 2008 9:57 Transmit signal from FPGA#1 to FPGA#2 |
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Hi
There are 2 FPGAs in my platform.
Signals from FPGA#1 to FPGA#2 are clocked by the "same frequency" and "not the same clock source".
Signals should be captured by FPGA#2 correctly.
How can I safely handle clock phase issue?
Please give me some ideas.
thank you so much!
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j_andr
Joined: 30 Mar 2008
Posts: 90
Helped: 15
Location: europe
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| 21 Aug 2008 10:14 Re: Transmit signal from FPGA#1 to FPGA#2 |
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| richardwli wrote: |
| /.../clocked by the "same frequency" and "not the same clock source" |
if you really have 2 clock sources you cannot be sure you have
the same frequency, or you can be sure you have 2 different rather;
if you have an external [ext. to the fpga's] clock generator send the
clock signal to both chips, if fpga1 is a clock source send the clock and
data to fpga2;
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KHOUBEIB
Joined: 19 Aug 2008
Posts: 3
Location: TUNISIA
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| 21 Aug 2008 11:43 Transmit signal from FPGA#1 to FPGA#2 |
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| hi , use some kind of communication protocole between them for exemple I2C, SPI or something like that
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avimit
Joined: 16 Nov 2005
Posts: 415
Helped: 68
Location: Fleet, UK
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| 21 Aug 2008 14:29 Re: Transmit signal from FPGA#1 to FPGA#2 |
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In your case the cloks going into FPGA1 and FPGA2 will be treated as Async. i.e even though they are theoritically same freq, they will have diff freq for practical reasons, and of course different phase. So you should use may be handshaking, or may be Fifo interface to transfer data from one FPGA to other. If its a serial data, then you just need Re-sync FFs in each FPGA for Sync.
Kr,
Avi
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richardwli
Joined: 24 Jun 2008
Posts: 3
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| 22 Aug 2008 2:14 Re: Transmit signal from FPGA#1 to FPGA#2 |
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| avimit wrote: |
In your case the cloks going into FPGA1 and FPGA2 will be treated as Async. i.e even though they are theoritically same freq, they will have diff freq for practical reasons, and of course different phase. So you should use may be handshaking, or may be Fifo interface to transfer data from one FPGA to other. If its a serial data, then you just need Re-sync FFs in each FPGA for Sync.
Kr,
Avi |
thanks guys
My data bus on interface are parallel
I think Avi's suggestion is applicable => Async FIFO interface method
Async FIFO has 2 clocks, one for input the other for output
for this case,
Does the clock of FPGA#1 need to be an input of FPGA#2 's FIFO interface?
or FPGA#2 can have a clock locally which is the same freq as the clock of FPGA#1?
thanks for your comment
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