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ASIC_intl
Joined: 18 Jan 2008 Posts: 199
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21 Aug 2008 8:19 FIFO problem |
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| Suppose Data is coming at the input of a FIFO with an average rate of 50 words per 100 clocks (average write rate). The MAXIMUM rate of data coming to FIFO input is 7 words per 10 clocks. The reading rate at the reading side of the FIFO is that in two clock cycles it can read one word only. Among the two clock cyles for reading the reading operation of the single word occurs only in first clock cycle and not in second clock cycle.Can u calculte the size of FIFO needed for this?
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rjainv
Joined: 18 Feb 2007 Posts: 147 Helped: 14 Location: Bangalore, India
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21 Aug 2008 8:43 FIFO problem |
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Lets consider the worst case scenario,
Atmost 7 words can come per 10 cycles. Lets say starting from fifo empty, we saw 7 cycles each having a word then followed by 3 cycles with no word - so that maximum word rate holds true.
So at 7th cycle, we are writing 7th word into the fifo. By this time the read side had 7 cycles to read ( assuming synchronous fifo). When the first word was written on 1st cycle, read side can read it at 2nd cycle at the earliest. So in 6th cycle, its reading 3rd word, and 4th word would be read in 8th cycle.
So going back to 7th cycle, when write side gets 7th word, there are 6(written)- 2 ( read) entries in fifo. So minimum depth that it should have is 4 + 1 ( being written in 7th fifo) in order to not overflow or cause write side to stall.
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ASIC_intl
Joined: 18 Jan 2008 Posts: 199
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22 Aug 2008 7:13 Re: FIFO problem |
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Hi rjainv
But after first 10 clock cycles the situation is 5 words have been read and 2 words are still there to be read in your size of 5 of the FIFO. Now again in next 10 cycles the worst case i.e. 7 words/ 10 cycles may occur and it can continue for upto first 40 cycles to maintain an average write rate of 50 words per 100 clock cycles. IN that case the size of 5 for the FIFO will not be an accurate value.
Please note that reading occurs as one word per two cycles. It is not necessarily that reading shoud occur in the first cycle among the two cycles as mentioned in my question. It is a mistake in the question.
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rjainv
Joined: 18 Feb 2007 Posts: 147 Helped: 14 Location: Bangalore, India
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22 Aug 2008 8:39 Re: FIFO problem |
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Yes you are right. I later realized that i had not taken correct worst case scenario.
Worst case scenario would be that write side writes maximum 50 words in 71 cycles, and by 71st cycle, read side would have read minimum 34 words ( read side saw word available in 2nd cycle, but started reading only second cycle of two cycle phase, i.e. 3rd cycle as counted from global count ).
So fifo sizing needs to be 50-34 = 16.
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megastar007
Joined: 20 Feb 2007 Posts: 82 Helped: 5 Location: Munich
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23 Aug 2008 9:13 Re: FIFO problem |
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i think minimum fifo depth size is 4. we should consider maximum rate.So, we can write only 7 words in 10 clk cycles.This can be random so in 20 clk cycles we can write maximum 14 words. in reading side,only 10 words are read in 20 clk cycles..so minimum depth is 4.
correct me if i am wrong
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ASIC_intl
Joined: 18 Jan 2008 Posts: 199
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28 Aug 2008 7:02 Re: FIFO problem |
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| I think solution by jainv is correct
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