craftor
Joined: 18 Aug 2008
Posts: 23
Helped: 2
Location: China
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 20 Aug 2008 14:12 Re: Pulse detection techniques |
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Here is an example about ADC0809, hope it help you . Craftor
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity ADC0809 is
port ( d : in std_logic_vector(7 downto 0);
clk,eoc : in std_logic;
clk1,start, ale,en: out std_logic;
abc_in :in std_logic_vector(2 downto 0);
abc_out :out std_logic_vector(2 downto 0);
q : out std_logic_vector(7 downto 0));
end ADC0809;
architecture behav of ADC0809 is
type states is ( st0,st1, st2, st3, st4,st5,st6);
signal current_state, next_state:states:=st0;
signal regl :std_logic_vector(7 downto 0);
signal qq:std_logic_vector(7 downto 0);
begin
com:process(current_state,eoc)
begin
case current_state is
when st0=>next_state<=st1;ale<='0';start<='0';en<='0';
when st1=>next_state<=st2;ale<='1';start<='0';en<='0';
when st2=>next_state<=st3;ale<='0';start<='1';en<='0';
when st3=> ale<='0';start<='0';en<='0';
if eoc='1' then next_state<=st3;
else next_state<=st4;
end if;
when st4=> ale<='0';start<='0';en<='0';
if eoc='0' then next_state<=st4;
else next_state<=st5;
end if;
when st5=>next_state<=st6;ale<='0';start<='0';en<='1';
when st6=>next_state<=st0;ale<='0';start<='0';en<='1';regl<=d;
when others=> next_state<=st0;ale<='0';start<='0';en<='0';
end case;
end process;
clock:process(clk)
begin
if clk'event and clk='1' then qq<=qq+1;
if QQ="01111111" THEN clk1<='1'; current_state <=next_state;
elsif qq<="01111111" then clk1<='0';
end if;
end if;
end process;
q<=regl; abc_out<=abc_in;
end behav;
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