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xtcx
Joined: 22 Dec 2007
Posts: 138
Helped: 5
Location: India
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 20 Aug 2008 6:15 How to generate a clock of 64KHz from FPGA in vhdl?. |
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| Guys for my project I need to use a 64KHz and 2048KHz clock for codec as its bit clock. So how can we divide and get 64KHz\2048KHz from 80MHz system clock in Xilinx Virtex4 FPGA. I know a lot of clock divider has already been described, but I still can't get a clear fact,most of the divder programs usually don't generate 50% duty cycle or rather not working. For my part 50% duty is important.Got any ideas?, plz share. Thanks in advance.
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craftor
Joined: 18 Aug 2008
Posts: 23
Helped: 2
Location: China
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| 20 Aug 2008 14:17 How to generate a clock of 64KHz from FPGA in vhdl?. |
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Hers is an easy example about clock division which is 50%duty cycle, hope it will help you . Craftor
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity clkdiv is
generic ( n : integer :=10);
port (
clkin : in std_logic;
clkout : out std_logic);
end clkdiv;
architecture arc of clkdiv is
signal clk_tmp : std_logic := '0';
signal cnt : integer := 0 ;
begin
process (clkin,cnt) begin
if (clkin'event and clkin='1') then
cnt <= cnt + 1;
if ( cnt = n-1 ) then
clk_tmp <= not clk_tmp;
cnt <= 0;
end if;
end if;
end process;
clkout <= clk_tmp ;
end arc;
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xtcx
Joined: 22 Dec 2007
Posts: 138
Helped: 5
Location: India
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| 21 Aug 2008 4:58 Re: How to generate a clock of 64KHz from FPGA in vhdl?. |
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| Yeah!, thanks for your approach craftor, but the divider program although provides 50% duty cycle but still how can you get the desired freq of 2.048 MHz from a 20MHz?. If you divide the clock of 20MHz by 10, then you should get 2MHz not 2.048MHz.But I want to get 2.048 MHz or 2048 KHz clk from an input clk of 20MHz. Do you understand my case?.
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avimit
Joined: 16 Nov 2005
Posts: 415
Helped: 68
Location: Fleet, UK
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| 21 Aug 2008 8:42 Re: How to generate a clock of 64KHz from FPGA in vhdl?. |
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I dont think that what you want can be done using a pure digital logic design. Since the frequency you want is not a factor of the frequency you have, I am almost certain that you need some thing else than digital logic.
64Khz shouldn't be a prob from 80Mhz as 80Mhz/64Khz is a whole number and that too even, so you will and can get a 64Khz clock from 80Mhz clock with 50% duty cycle using pure digital logic design
Kr,
Avi
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craftor
Joined: 18 Aug 2008
Posts: 23
Helped: 2
Location: China
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| 22 Aug 2008 10:24 How to generate a clock of 64KHz from FPGA in vhdl?. |
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Agreed with Kr,Avi.
The codes I have given above is just an example, if you want to get 64KHz, you have to write the codes by yourself.
GL!
Craftor
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penrico
Joined: 28 Aug 2001
Posts: 225
Helped: 8
Location: Argentina
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| 22 Aug 2008 12:32 Re: How to generate a clock of 64KHz from FPGA in vhdl?. |
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You can try divide in 4 steps.
First step divide by 9. The other 3 steps divide by 10.
The general division ratio will be:
(9+10+10+10)/4 = 9.75
So, if you have a 20Mhz clock
ClkOut = 20Mhz/9.75 = 2051 Mhz
Here you have how to do it, I don't test it. Please reply what do you think
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity clkdiv is
port (
clkin : in std_logic;
clkout : out std_logic
);
end clkdiv;
signal subcount : std_logic_vector[2 downto 0];
signal count: std_logic_vector[3 downto 0];
signal clk_tmp : std_logic;
architecture arc of clkdiv is
begin
process (clkin) begin
if clkin'event and clkin='1' then
if (count<9 and subcount=0) or (count<10 and (not subcount=0)) then
count<=count+1;
else
count<=(others=>'0');
clk_tmp<=not clk_tmp;
if (subcount<3)
subcount<=subcount+1;
else
subcount<=(others=>'0');
end if;
endif;
end if;
end process;
clkout <= clk_tmp ;
end arc;
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FvM
Joined: 22 Jan 2008
Posts: 2635
Helped: 431
Location: Bochum, Germany
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| 22 Aug 2008 19:53 Re: How to generate a clock of 64KHz from FPGA in vhdl?. |
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| Your suggesting a fractional divider. It may be solution if some additional clock jitter can be tolerated. We can't know, as no quality specification was given.
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