Mentor Graphic: Project Porting to another SoftWare (50pt)

EDAboard.com Forum Index -> PLD, SPLD, GAL, CPLD, FPGA Design -> Mentor Graphic: Project Porting to another SoftWare (50pt)

Author

Message

sadid

Joined: 24 Oct 2006
Posts: 122
Helped: 2

17 Aug 2008 12:56 Mentor Graphic: Project Porting to another SoftWare (50pt)

I've Design my project in Mentor Graphics/FPGA Advantage Package.........it's a really good S.W.
but now I need to implement These modules in my design using Mega functions and IPs......:
1.One or Two Soft Core
2.an CAM/RAM Memroy
3.Ethernet Interface
How can I port my project from FPGA Advantage to qu(at)rtus or ISE?
or How can I implement these IPs in my design?
or any suggest that might help....
Thank.

j_andr

Joined: 30 Mar 2008
Posts: 107
Helped: 20
Location: europe

17 Aug 2008 16:21 Re: Mentor Graphic: Project Porting to another SoftWare (50p

sadid wrote:

/.../How can I port my project from FPGA Advantage to qu(at)rtus or ISE?

if I understand your question correctly, you should:
- create your project with so-called black-boxes which are
'place holders' for ise/qu(at)rtus specific macros;
- add an attributes 'black box' for the modules if your tool requires it
[most probably yes];
- compile to generate an input for ise/qu(at)rtus place&route and assembler;
[verilog netlist for instance]
- generate with ise/qu(at)rtus required memories, interfaces [the body of your
'black boxes'];
add the netlist and tool [ise/qu(at)rtus] specific macros [coregen/megawizard] to
your project and compile;

black box is an entity/module with ports declarations only, without any body;
[without any logic]
---

Last edited by j_andr on 21 Aug 2008 9:10; edited 2 times in total

Google
AdSense
Google Adsense

17 Aug 2008 16:21 Ads

sadid

Joined: 24 Oct 2006
Posts: 122
Helped: 2

18 Aug 2008 5:24 Mentor Graphic: Project Porting to another SoftWare (50pt)

My Design in FPGA Advantage contains some component it has both entity and architecture...
I don't think that this approach is practical....do you have a related experience?
in addition I have a choice re-design my component in qu(at)rtus II v9 currently I've design my entity/architecture but I'm searching for faster approach...

j_andr

Joined: 30 Mar 2008
Posts: 107
Helped: 20
Location: europe

18 Aug 2008 8:34 Re: Mentor Graphic: Project Porting to another SoftWare (50p

sadid wrote:

/.../I don't think that this approach is practical/.../

it's a standard flow when:
1.you have to generate a loadable fpga image;
2.you use a third party synthesis software;
3.your design contains any vendor specific module
[pll/lvds/mamory...] which you can not describe in verilog/vhdl
and it's not in the software library;
if any of the above items is not true you do not have to follow
the flow;
---

sadid

Joined: 24 Oct 2006
Posts: 122
Helped: 2

21 Aug 2008 6:41 Mentor Graphic: Project Porting to another SoftWare (50pt)

Thank j_ander so I can generate a loadable image with FPGA Advantage.......then import it to qu(at)rtus II and add required modules to it and generate final image...is it true? is it possible?

j_andr

Joined: 30 Mar 2008
Posts: 107
Helped: 20
Location: europe

21 Aug 2008 7:47 Re: Mentor Graphic: Project Porting to another SoftWare (50p

sadid wrote:

I can generate a loadable image with FPGA Advantage/.../

not exactly;
you can generate a netlist with your tool, not an fpga image,
the netlist has to be imported to qu(at)rtus and merged with altera macro(s);
---

muhammad_ali

Joined: 26 Mar 2008
Posts: 43
Helped: 8
Location: Egypt

21 Aug 2008 12:07 Re: Mentor Graphic: Project Porting to another SoftWare (50p

in the HDL designer: in the right pane you can find the TASK pane: invoke xilinx core generator (or qu(at)rtus core generator).
choose then the library you need to create your IP then click Invoke core generator.
you will find a wizard that guide you with the available IPs. choose your IP then go in the other wizard steps.....
and tell me please if this is sufficient or not, also tell me if you faced any problems.