vandelay
Joined: 16 Aug 2007
Posts: 111
Helped: 2
Location: Norway
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 15 Aug 2008 18:18 Routing DDR2 bus |
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I am laying out a signal processing card involving a DDR2 SDRAM, and I have some questions regarding the routing of the bus.
I have started out with the data groups of a 16-bit wide device, and I have succeeded in wiring data bits, strobes, and bit masks to my FPGA using 20mm +/- 0.1mm long traces 5 mil wide with NO vias, solid ground plane directly below. The documentation I have read suggests grouping data bits with strobe and bit mask for every byte, as a 'byte lane', however I cannot separate the 16-bit bus into byte lanes without compromising (adding vias to the bus).
Since the data bus is fairly short (20mm) I hope I will get away with interleaving all 16 data bits and associated strobes/bit masks, into a single lane with approx 3x trace width spacing between signals at most points, and still use it at full speed (667MHz)
Can anyone with DDR2 layout experience give me a heads up on that?
I could use two 8-bit RAM for easier grouping of individual byte lanes, but this is a cost sensitive project so I would like to get away with only one RAM chip, thus a 16-bit device.
Also, I will not run into problems with skinning effects using 5mil wide 20mm long traces, right?
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