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frequency drift in PLL design

 
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buyan



Joined: 27 Jan 2005
Posts: 25


Post15 Aug 2008 4:32   frequency drift in PLL design

I have designed a PLL for 4000MHz output using a 20MHz REF from OCXO with synthesizer ADF4106. Loop filter is passive.

I use a divider to get three 20MHz REFs. One connects to Oscillator Scope, the second one is for PLL REF and the third one connects to a RS signal generator. I use a passive mixer to down converter the 4000MHz to 20MHz with LO from the RS signal generator. Then I connect the 20MHz output from the mixer to the Oscillator Scope too to compare with the REF 20MHz.

However, I found that the 20MHz output from the mixer is drifting during 12 hours continuously running watching period.

Please kindly advise what are the possible reasons? Thanks.
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