PSL Assertion for VHDL design

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uditkumar1983

Joined: 03 Dec 2006
Posts: 103
Helped: 4
Location: India

14 Aug 2008 8:48 PSL Assertion for VHDL design

Hi All,

I want to write assertion (in vunit) such that which can contain "if else" part of any process statement in PSL , My design is in VHDL.

Can anyone help me on this. Or you can share some examples on it.

Thanks & Regadrs,
Udit Kumar

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jonyRoyal

Joined: 24 Apr 2006
Posts: 35
Helped: 3

25 Dec 2008 11:20 Re: PSL Assertion for VHDL design

Hi,

vunit alu_assertion (alub(alub)) {
use work.packageCPU;

signal test_signal : std_logic_vector (TEST_SIZE -1 DOWNTO 0);

default clock is rose(clock);
Errorsatge: assert never {system.i_cpu.i_alub.t2 & system.i_cpu.i_alub.t3};
Errorfree: assert never {T2 or T2};

test_assert_forall: assert forall i in {0 to TEST_SIZE} : {T2 and T2 and test_signal(i)};
}

Thanks
Jagadeesh