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brunokasimin
Joined: 13 Jun 2008
Posts: 71
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 12 Aug 2008 14:24 Mentor Graphic HDL FpgAdv |
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| Is anyone out there expert in Mentor Graphic HDL Designer?
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no_mad
Joined: 10 Dec 2004
Posts: 242
Helped: 19
Location: Naboo
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| 13 Aug 2008 3:52 Mentor Graphic HDL FpgAdv |
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Hi bruno,
I'm not an expert but I've used it before.
Post you questions or doubts and I'll try to help you out.
-no_mad
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muhammad_ali
Joined: 26 Mar 2008
Posts: 44
Helped: 8
Location: Egypt
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| 13 Aug 2008 6:54 Re: Mentor Graphic HDL FpgAdv |
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Hi bruno,
what are your questions? i am dedicated in my work for the HDL Designer.
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sadid
Joined: 24 Oct 2006
Posts: 110
Helped: 2
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| 17 Aug 2008 5:50 Mentor Graphic HDL FpgAdv |
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I'm currently using it.
I Think it's far better than qu(at)rtus and ISE but now I have trouble for using IP and Mega Function for example I want to use CAM/RAM mega function and also Ethernet and a soft core but I can't ...
is it possible to port it's project to other S.Ws?
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brunokasimin
Joined: 13 Jun 2008
Posts: 71
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| 18 Aug 2008 13:55 Re: Mentor Graphic HDL FpgAdv |
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Hello no_mad,
Currently i'm learning a soft-core processor/IP-Core called ZPU. I've downloaded it from www.opencores.org. My task is to import all the ZPU Processor .vhd files in a library in Mentor HDL Designer.Now i need to implement it in FPGA @ltera Cyclone.To establish a connection btw the soft-core processor and fpga, i need the wishbones interface. My question is should i includes the wishbone .vhd files in the same library , where i put my .vhd files of zpu processor?
Thx
Added after 9 minutes:
hello sadid,
i'm also still learning about a soft-core processor, called zpu, which i've downloaded from www.opencores.org.So at the moment i cant help you.
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craftor
Joined: 18 Aug 2008
Posts: 23
Helped: 2
Location: China
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| 21 Aug 2008 2:10 Mentor Graphic HDL FpgAdv |
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| If you want to implement a project in @ltera's FPGA, you'd better use qu(at)tus, it will save a lot of problems.
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muhammad_ali
Joined: 26 Mar 2008
Posts: 44
Helped: 8
Location: Egypt
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| 21 Aug 2008 9:11 Re: Mentor Graphic HDL FpgAdv |
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hello craftor,
it is a comparative issue 
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brunokasimin
Joined: 13 Jun 2008
Posts: 71
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| 04 Oct 2008 1:42 Re: Mentor Graphic HDL FpgAdv |
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity hello_world is
port (
clk : in std_logic;
-- reset : in std_logic;
led : out std_logic
);
end entity hello_world;
--
architecture rtl of hello_world is
constant CLK_FREQ : integer := 20000000;--20000000
constant BLINK_FREQ : integer := 1;
constant CNT_MAX : integer := CLK_FREQ/BLINK_FREQ/2-1;
signal cnt : unsigned(24 downto 0);
signal blink : std_logic;
begin
process(clk)
begin
-- if reset <='1' then
-- blink <='0';
if rising_edge(clk) then
if cnt=CNT_MAX then
cnt <= (others => '0');
blink <= not blink;
else
cnt <= cnt + 1;
end if;
end if;
end process;
led <= blink;
end architecture rtl;
I tried to run this programm to blink led in both qu(at)rtus and fpgadvantage from mentor, but it was only successfull in qu(at)rtus..anyone has idea about this??
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karikalan_t79
Joined: 20 Oct 2008
Posts: 100
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| 22 Oct 2008 4:25 Re: Mentor Graphic HDL FpgAdv |
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| mentor only give you edf netlist, later then you have create another project in qu(at)rtus, use this edf file as top design and that is it
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