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jitendravlsi
Joined: 21 Jul 2008
Posts: 5
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 12 Aug 2008 7:44 floorplan |
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If somebody faces congestion problem after floorplan, then how he can remove congestion without changing aspect ratio and utilisation factor?
Thnx in advance
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MarcS
Joined: 30 Jun 2008
Posts: 79
Helped: 10
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| 14 Aug 2008 8:29 Re: floorplan |
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| What do you mean by 'floorplan'? Are you talking about the total size and shape of the single block/chip you are working on, or are you referring to the placement of multiple floorplan regions with standard cell areas between the floorplan blocks?
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Nir Dahan
Joined: 19 May 2008
Posts: 65
Helped: 6
Location: Munich, Germany
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| 19 Aug 2008 19:43 floorplan |
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try to reduce wide buses, and many wires crossing the chip.
- if you got large register banks, try reducing the width of a register (this might mean to change the register protocol handling)
- if you access a lot of wide SRAMs, think about maybe you could serialize the information. try to place SRAMs close to the blocks which are using them.
- Think about replication. it is sometimes wise to duplicate a block and spend more area and power on logic and flops. later you will save big time on the amount of wires crossing the chip and you will also save power due to buffer reduction (needed to drive the long wires)
the above steps should be done on the concept phase of your design. although it is never too late.
good luck,
ND.
http://asicdigitaldesign.wordpress.com
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hiral.kotak
Joined: 28 Aug 2008
Posts: 62
Helped: 7
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| 28 Aug 2008 10:09 Re: floorplan |
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Hi,
you can analyze the macro placement. Try to place the macros with proper flyline analysis i.e. examines the connections from macro to macro, stdcell and i/os. Try to reduce redundent blockage creation during planning.
This may help you.
Thanks.
HAK.
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sowmya005
Joined: 20 Nov 2006
Posts: 44
Helped: 1
Location: INDIA
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| 11 Sep 2008 10:17 Re: floorplan |
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Floorplan is an iterative process. This affects all the other steps of Physical design.
Sometimes, you will need to do according to the architecture defined for the design.
If not, then you have to do some iterations.
First run the placement in floorplan mode. You can take this as the first iteration. Change the placement of macros or partitions if you have.
If you have macros in your design, you will need to check its lef, find the power pin metal layers used.
Place the macro accordingly that the metal layer conventions are followed, ie horz M1, M3
vert-M2, M4.
Place the macros towards the edge.
These are few important things to consider.
Thanks
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jitendravlsi
Joined: 21 Jul 2008
Posts: 5
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| 11 Sep 2008 15:48 Re: floorplan |
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| Thanks u all.....
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papertiger
Joined: 28 Dec 2002
Posts: 65
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| 12 Sep 2008 4:05 Re: floorplan |
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1, calculate the routing resource.
In most case, this is the best way to remove congestion.
You need to consider power route scheme, PG via drops width,
consider 90 degree rotate the chip.
2, If the congestion is local and minor, use placement density constraints
3, analysis the logic , understand where the congestion come from ,
rewrite the verilog code.
4, redo floorplan (macro placement, soft constraints. module placement.etc)
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