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darrenbkl
Joined: 13 Jul 2008
Posts: 13
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 08 Aug 2008 9:35 Ripple Blanking I/O |
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| Hi all,have a question here is that,what is the function RBI,RBO and LT pin on the 7447 BCD-7segent decoder IC? It seems to suppressed zero on the 7 segment display,but I don't know how it works. About the LT, I only know has to connect to VCC, can anyone explain me? thx : )
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Arkham00
Joined: 08 Aug 2008
Posts: 4
Helped: 1
Location: Italy
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| 08 Aug 2008 10:42 Re: Ripple Blanking I/O |
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LT is a LAMP TEST input. It's active low so when at logic level 1, it has no effect; when at logic level 0, every output is active so you can check if a segment or an output is broken.
RBI is RIPPLE BLANKING INPUT is used in multi-digit display and should be connected to the RBO of the previous digit (the digit to the left). In this way, you may avoid showing trailing "0" if not needed as you do in manual number writing. In this way, for example, the multidigit number "00123" will show as "__123" while "02034" will show as "_ 2034" (where "_" is to be intended as an off digit). This trick was in use when digital circuits were not so intelligent as now with microcontrollers.
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darrenbkl
Joined: 13 Jul 2008
Posts: 13
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| 08 Aug 2008 13:00 Re: Ripple Blanking I/O |
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cool,thx. I m a newbie in electronic stuff,currently still doing flip flop and counter : (
I try to connect a 7490 counter --- 7447 --- 7 segment display using multisim,it works. But why when i switch on the circuit, the display appear unstable? I mean when the display change from a number to the other, let's say from 4 to 5, in between transition there is some unstable state of the display. is it cause by propagation delay of the serial ripple counter connection?
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Arkham00
Joined: 08 Aug 2008
Posts: 4
Helped: 1
Location: Italy
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| 08 Aug 2008 14:17 Re: Ripple Blanking I/O |
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Don't think so. Propagation time in standard TTL is very fast. Maybe some pin left open even if in TTL logic, an unconnect pin should be read as '1'.
Try posting the schematic.
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darrenbkl
Joined: 13 Jul 2008
Posts: 13
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| 09 Aug 2008 7:37 Re: Ripple Blanking I/O |
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Added after 35 minutes:
http://pdf1.alldatasheet.com/datasheet-pdf/view/51095/FAIRCHILD/74LS90.html
this is the DM74LS90 datasheet, where i was confuse by the 7490 schematic diagram. the clock input B is into 2nd and 4th flip flop only ,and 2nd FF's J input is determine by 4th FF's Q bar output. and 4th FF K input is determine by its Q output.
how does this work basically i dun understand.
thx for guiding  
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Arkham00
Joined: 08 Aug 2008
Posts: 4
Helped: 1
Location: Italy
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| 09 Aug 2008 8:56 Re: Ripple Blanking I/O |
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The circuit seems basically correct.
Just some note:
* the clock frequency of 1kHz is very high for a display. You'll be unable to see the number changing. Try with much lower frequency like 1 or 2 Hz
* the BI/RBO pin is a strange input/output pin. Leave it unconnected
* try the same with LT and RBI. In TTL logic (like LS family), an unconnected pin is equivalent to a logic "1" (but this is not true for CMOS logic where every pin mus be connected to a secure digital level)
* in the real circuit, put a 0.1uF bypass ceramic capacitor as near as possible to the poer pins of the device
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darrenbkl
Joined: 13 Jul 2008
Posts: 13
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| 09 Aug 2008 17:57 Ripple Blanking I/O |
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| wat does the 0.1uF cap do? u mean place it near "power" pin?
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Arkham00
Joined: 08 Aug 2008
Posts: 4
Helped: 1
Location: Italy
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| 09 Aug 2008 21:18 Re: Ripple Blanking I/O |
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Yes, sorry ... I meant "power" pins.
In real-world circuits, it's suggested to put a 0.1uF capacitor between VDD and VSS of a device every few device to filter high frequency noise generated by fast switching logic devices.
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darrenbkl
Joined: 13 Jul 2008
Posts: 13
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| 12 Aug 2008 5:40 Ripple Blanking I/O |
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| A clock pulse with 1kHz frequency,which is a 50% duty cycle square, that means the period of the wave is 1ms right? But 1 pulse is consist of a high and low , or high and low are consider as a pulse separately?
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