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laststep
Joined: 24 Jan 2007
Posts: 59
Helped: 7
Location: Malaysia
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 08 Aug 2008 1:23 Flip-Flop initial value at startup? |
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Hi,
I have a doubt for the FF startup value hope can get the answer through this forum.
Let said we build a positive clock edge Flip-flop with preset and clear control on our die.
If the preset and clear signal not being active at the startup and the clock signal maintain as low,
what would be the output of the FF? Would it be some value either '1' or '0' or it would be undefined ('X')?
Someone told me that due to the die characteristic, the FF will have some initial value even it not being preset and clear at the startup with the clock never toggle before. Is it true?
Thanks.
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flatulent
Joined: 19 Jul 2002
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Location: Middle Earth
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| 08 Aug 2008 1:49 Re: Flip-Flop initial value at startup? |
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Due to different transistor parameters caused by variations in processing parameters across the die, you do not know which way the device will power up to.
This is why many circuits have a "power up reset" circuit.
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apallix
Joined: 07 Aug 2008
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| 08 Aug 2008 2:07 Re: Flip-Flop initial value at startup? |
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In short, that is true. But you will not know whether it will end up as logic '1' or '0'.
Electrically, even if it initially starts up in an intermediate voltage level (i.e, in metastable state), there will be enough noise and parameter variation in the latch feedback to push it towards either 'VDD' or 'GND'
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arman_arian2005
Joined: 20 Oct 2006
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| 08 Aug 2008 5:32 Re: Flip-Flop initial value at startup? |
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I encountered this problem recently too.
I intend to simulate a three state phase detector using spice. I got the output always X, due to invalid initial value. So what can I do to solve this problem?
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apallix
Joined: 07 Aug 2008
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| 08 Aug 2008 5:45 Re: Flip-Flop initial value at startup? |
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| Quote: |
| I intend to simulate a three state phase detector using spice. I got the output always X, due to invalid initial value. So what can I do to solve this problem? |
You can assert the reset pin of the flops that you are using to implement the phase detector to start in a known state.
For simulation in spice, you can also use the ".ic" statement to initialize the internal latch node of the flops to the desired state.
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laststep
Joined: 24 Jan 2007
Posts: 59
Helped: 7
Location: Malaysia
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| 08 Aug 2008 9:11 Flip-Flop initial value at startup? |
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So, the flip-flop will eventually stay to '1' or '0' at initial stage.
If i try to model a flip-flip, can i set the initial value to either '0' or '1' in this case?
Something like this:
initial begin
assign q = 1b'1;
if(reset){
q = 1'b0;
}
elsif(posedge clock and clock = 1){
q = d;
}
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apallix
Joined: 07 Aug 2008
Posts: 19
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| 09 Aug 2008 6:12 Re: Flip-Flop initial value at startup? |
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| Quote: |
initial begin
assign q = 1b'1;
if(reset){
q = 1'b0;
}
elsif(posedge clock and clock = 1){
q = d;
} |
You could initialize your logic simulations this way, but in real designs, you would use a reset signal to perform the initialization.
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FvM
Joined: 22 Jan 2008
Posts: 2635
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Location: Bochum, Germany
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| 09 Aug 2008 10:49 Flip-Flop initial value at startup? |
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Many FPGA families are assuring a defined register state after power on reset. The tools are synthesizing a correct power on state from Verilog initial blocks or VHDL signal initialisation. It's definitely working with @ltera FPGA and qu(at)rtus.
Of course, there can be many reasons to use an explicite reset anyway.
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lordsathish
Joined: 11 Feb 2006
Posts: 244
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Location: Asia
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| 11 Aug 2008 5:42 Re: Flip-Flop initial value at startup? |
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This problem may also be due to powering up.
Our power supplies usually dont to Vdd the moment we switch ON.
There is a finite rise time to it. I also encountered this problem while i was trying to build a Digital clock the counter when powered up wont go to 0000 state.
Please correct me if i'm wrong.
Thank you.
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FvM
Joined: 22 Jan 2008
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Location: Bochum, Germany
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| 11 Aug 2008 7:42 Flip-Flop initial value at startup? |
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Reviewing the discussion, I found that it's mixing unrelated problems, e. g. behavior of FF as such, behaviour of FPGA and simulation. Your adding the topic of different supply voltage rise.
- A FF in general, also a counter, e. g. as a TTL or CMOS logic device, usually has no power-on-reset (POR). In most cases, it has an accidental initial state. A POR should be designed in the circuit, preferably in a way that's unsensitive to slow and non-monotonic supply voltage rise and such issues.
A FF in a CPLD or FPGA mostly has a POR respectivly a defined power-on state.
In simulation, an unknown state is assumed for all registers usually. Thus an additional initialisation of registers for simulation may be necessary to make the design work at all, even for a simple /2 clock divider.
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laststep
Joined: 24 Jan 2007
Posts: 59
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Location: Malaysia
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| 12 Aug 2008 1:08 Flip-Flop initial value at startup? |
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HI FvM,
Thanks for your review. i'm more interest in the CPLD or FPGA device. These device do have the POR but i believe that not all the FF are being reset after the POR trigger.
Most probably if we doing a unknown state checking on all the FF, we will still found some FF with unknow value. If we doing a 'X' checking in all our design, this FF will cause a false warning. But this 'x' value is acceptable cause is neither the contention nor design fault. So i just wonder if we can set a initialize value for these FF and of cause i would like to know that in real case are the FF also having some initialize value for those that didnt get reset by the POR.
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