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vinun_7
Joined: 11 Feb 2007
Posts: 21
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 04 Aug 2008 5:25 Simulation hanging.... What can be the causes..? |
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My question is related to verification.
If u r running a simulation (module level or full chip) and u have already made sure that
- clk/reset and other connectivities are okay
- the chip has booted properly
But the simulation hangs.
- Ur simulation time is not proceeding only delta is proceeding.
What could have gone wrong? What can be the things we can look for debugging...?
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avimit
Joined: 16 Nov 2005
Posts: 415
Helped: 68
Location: Fleet, UK
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| 04 Aug 2008 9:05 Simulation hanging.... What can be the causes..? |
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One of the possible causes of simulation hang is a what is called signal deadlock. It happens where 2 processes are involved, and one signal say A_sig in a process say process_A is waiting for a change in a signal, say B_sig in the another process, say process_B, and B_sig is waiting for a change in A_sig.
If you are working in VHDL, then improperly used wait statements are the most frequent cause of a simualtion hang.
hope it helps,
Kr,
Avi
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vinun_7
Joined: 11 Feb 2007
Posts: 21
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| 04 Aug 2008 9:45 Simulation hanging.... What can be the causes..? |
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| Thanks Avi...
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santhosh007
Joined: 27 Aug 2008
Posts: 53
Helped: 14
Location: Bangalore
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| 28 Aug 2008 9:51 Re: Simulation hanging.... What can be the causes..? |
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it could be with zero delay gate oscillation
If its NCverilog run with this option +ncgateloopwarn +ncaccess+c...
when it hangs.. interupt the simulation(Ctrl+c) then
ncsim> drivers -active
this tells you active drivers.. you add #1 for that cell.
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