clock domain crossing

EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital) -> clock domain crossing

Author

Message

ASIC_intl

Joined: 18 Jan 2008
Posts: 199

31 Jul 2008 8:52 cross clock domain design

Why do we use FIFO to synchronize datapaths instead of flop synchronizers during clock domain crossing?

kvingle

Joined: 05 Nov 2007
Posts: 167
Helped: 16
Location: Mumbai, India.

31 Jul 2008 10:43 data coherency issues in clock domain crossing

flop based synchronizers are suitable when number of signals crossing **** domain are limited say 2-3. when you are transferring data of 8, 16 or more bits, FIFO is more convenient & reliable way.

ASIC_intl

Joined: 18 Jan 2008
Posts: 199

31 Jul 2008 11:25 clock domain crossing

What is the reason of FIFO being a more reliable way when the date is of more bits like 8, 16 etc. Do you know any document location regarding this?

kvingle

Joined: 05 Nov 2007
Posts: 167
Helped: 16
Location: Mumbai, India.

31 Jul 2008 11:27 synchronizer flops

refer to digital design principles and practice By John Walkerly.
It has good theory on synchronizers .You can get a digital copy in ebooks section on edaboard.

ASIC_intl

Joined: 18 Jan 2008
Posts: 199

31 Jul 2008 12:22 flop +meta stable +syncronizer

What is the web location for this digital copy of John Walkerly in edaboard ?

You did not answer the technical question thrown by me.

kvingle

Joined: 05 Nov 2007
Posts: 167
Helped: 16
Location: Mumbai, India.

31 Jul 2008 12:44 clock domain crossing data bus

The book
http://www.edaboard.com/viewtopic.php?t=149432

another quick reference
http://www.edn.com/article/CA310388.html

vipulsinha

Joined: 09 Nov 2005
Posts: 43
Helped: 3

01 Aug 2008 17:51 client clock in domain not correct

when the no of signals crossing the clock domain is more that 2/3 i,e if it is 8, 16 more then you cannot use 2 flops as there is no gurantee that even if you use 8/16 flops for each bit to syncronize will be sampled correctly.

The best way if you want to use 2 flops in this case is to convert the bibary to gray code as only one bit will be changing at a time. Suppose u have like 4 bits ..

so from 0000---> 1111 there are 4 bits changing so each bit cannot be sampled with 2 flops effectively id u use 2 flops.

Secondly if there is data rate is concerned then you need a buffer mechanism so you need FIFO . 2 Flops wont do .

So for control signal we use 2 flops and in data matching and synchronizing we use FIFO ..

uditkumar1983

Joined: 03 Dec 2006
Posts: 103
Helped: 4
Location: India

02 Aug 2008 13:32 clock domain metastable

Hi All,
If u r using synchronizer for data signal then there willl be problem for data conherency.

Second using double flop synchronizer will require more gate count (For high data width)

ASIC_intl

Joined: 18 Jan 2008
Posts: 199

05 Aug 2008 16:12 clock domain wrong

Hi vipulsinha

If your control path is a 8 or 16 bit bus. Will you also use then use 2 flop synchronizer?

Why do you think for a 8/16 bit data bus if we use 2-flop synchronizer for each bit, it will not work? Why will not it work properly?

For uditkumar1983 :

What is data coherency?

Google
AdSense
Google Adsense

05 Aug 2008 16:12 Ads

apallix

Joined: 07 Aug 2008
Posts: 19
Helped: 2

07 Aug 2008 8:01 cross clock domain double buffering

my take is:

lets say there is an asynchronous bus A[3:0] that is being sampled by a different freq domain with double flops and the sampled output is Ax[3:0].

Lets say A[3:0] changed from 0000 to 1111 with all the bits changing around the same time. On account of the asynchronous nature of the signals, Ax[3:0] may change from 0000 to 0101 in one cycle and the next cycle 0101 changes to 1111. So, the intermediate value on Ax 0101 is illegal. Ax should have changed from 0000 to 1111 without any intermediate illegal value.

So, when we have a bus, we use a FIFO. If it is a single control signal, there is no case of illegal intermediate state since there are only two states.

comments welcome.

ASIC_intl

Joined: 18 Jan 2008
Posts: 199

07 Aug 2008 8:39 cross clock domain change double synchronizer

hi apallix

Suppose there is a one bit that is being synchronized by two flops. Suppose in first clock domain it is logic high. Now when it enters new clock domain due to metastability it may not be properly trnsferred and appeared as an erroneous value of logic zero as an intermediate state. So in the way your 4 bit bus prduces an illegal state 0101, here in a similar way in new clock domain we get appearance of an illegal state of logic zero instead of the logic 1. Now after some time it will go to its propoer state of logic one in the same way as your 0101 state will reach the legal state 1111.

bibo1978

Joined: 01 May 2004
Posts: 229
Helped: 6

07 Aug 2008 9:08 problems connecting to domain as clock incorrect

FIFO is used when you need to transfer data from one clock domain (clock domain at which you store data) to another clock domain, it grantees that the data will cross from that domain to the other (smoothly) if the Asynchronous FIFO is designed right (Async FIFO usually will include Synchronizers or similar approaches) FIFO will introduce latency to assure that the data crosses the domain approriately
The syncronizer on the other hand is a way to avoid metastability that can be caused by sampling an asynchronous "in a slower clock" (signal) to another time domain (faster), the synchronizer is a way to avoid sampling at intermediate state of a signal which can cause metastability it only decrease the proabability of metastability (there is a mathematical theory behind this I think it is called Burden thoery) so if you add more FFs to synchronizer you propably can sample a signal with less probpility of trapping into some intermediate state, for instance with three flips you get an even lower probability, there is no grantee that if you sample a bus using synchronizers you will get the actual value so synchronizers are only for metastability problem, that's because you can sample a signal with a synchronizer (or more) but you can get the value a data bus with a synchronizer because you don't know for sure that when you are sampling each synchronizer is sampling the data bus on its valid state (after setup time and before transit time)
The concept is totally different (to read a data) you need to know when you are sampling it (FIFO do this because it uses the first clock domain to register the Data and hold it valid until it is read), internally the FIFO will send a cross signal to its counters which will run asynchronously (so you can't use a simple binary counter in FIFO, usually you need a grey counter or another complex counter that can't have multiple transit of bits. Async FIFO design can be very tricky

apallix

Joined: 07 Aug 2008
Posts: 19
Helped: 2

07 Aug 2008 21:02 clock domain crossing with ffs

Hi ASIC_intl,

In my example, I am assuming that by using a double flop, the probability of failure due to metasatibility is very little. Therefore, the sampled output has proper logic levels. If the probability of failure is still high, you may need to add more flops in the synchronizer until the probability of failure is acceptable for the specific design. When there is metastability in the first flop, the probability of metastability in the second flop is greatly reduced and so on.

In the example that I had, if A changes from 0000 to 1111 at the same time as the sampling clock rises, there could very well be metastability in the first synchronizer flops. And when the second synchronizer flop samples the output of the first flop, it may see values 0101 (for example) due to the metastability in the first flop. However, by the second sampling cycle at the first flop, the input data would have stabilized and it would see perfect 1111. So, ultimately Ax will be 1111 but with intermediate illegal logic state.

ASIC_intl

Joined: 18 Jan 2008
Posts: 199

08 Aug 2008 10:13 clock domain crossing digital design

Hi apallix

In your example u have an intermediate illegal state 0101 of four bits. Let us take your MSB (left most bit) out of these four bits. Due to metastability it is getting an illegal intermediate vaue of zero rather than legal value of high. So this is also problemful for one bit. I want to say this only in my last reply. Do u understand now? Comment on this.

apallix

Joined: 07 Aug 2008
Posts: 19
Helped: 2

08 Aug 2008 19:15 clock domain crossing techniques

Quote:

Hi Asic_intl,
If we consider only the MSB in my example, there is no logic problem, only latency problem. If we were monitoring only the MSB in the sampling domain, we will observe the transition from '0' to '1' one cycle late in the event of metastability.

Ax[3] (w/o metastability): 0 -> 1 -> 1
Ax[3] (w/ metastability) : 0 -> 0 -> 1

The logic on the sampling side will just assume that the asynchronous input just came late.

In the case of the bus Ax[3:0]:
Ax (w/o metastability) : 0000 -> 1111 -> 1111
Ax (w metastability on bits 3 & 1) : 0000 -> 0101 -> 1111

If we are monitoring Ax[3:0] we expect them to be coherent as they transition from one freq domain to the next. In the example above, bits 3 and 1 had metastability and ended up as '0' while bits 2 and 0 either did not have metastability or did have metastability but ended up as '1'. The sampling side logic sees 0101 on bus Ax which it should not have.

Basically, when we are crossing frequency domains, a hit on latency is acceptable but lack of coherency in the data bits is not acceptable.

bibo1978

Joined: 01 May 2004
Posts: 229
Helped: 6

08 Aug 2008 21:30 double flop synchronizer book

guys metastability is not that you read wrong data it is that your circuit might work in non descrete mode simply your FF is more or less some transistors they are designed in such a way that it will usually be saturated or switched off (on-off) however there is some input signal that might inteosice invalid input let's say in TTL a zero is between 0-0.2 v and one is between 4.7 and 5.2 v an input below 1.4v is considered a zero and an input above 2.4 is considered a one anyway this circuit is still an analog circuit at some voltage this circuit will produce some signal blbetween the 0.2 and 4.7 and it may hang because the transistors might be in active state ( not saturated or switched off),it might stay there for a while, to note that this input exactly will differ from a gate to another ,that's the metastability it is state of inaccuracy of output and it is meta stable. This concept is mathematically valid for a lot of issues when you try to make a descrete result from a non descrete input it has some probability and it might happen to you in life when you are in some critical descision let's say u are in a railway of a train that by accident you just passed the train gate and it closes and now you have to decide what to do go forward or backward u might hang on there for a while thinking
that's metastability it is not only violation of setup time only it is less than this

apallix

Joined: 07 Aug 2008
Posts: 19
Helped: 2

08 Aug 2008 21:57 asynchronous clock domain

Quote:

let's say u are in a railway of a train that by accident you just passed the train gate and it closes and now you have to decide what to do go forward or backward u might hang on there for a while thinking

Thats a good example.

Metastable means exactly what it says, "meta"-"stable".

If you were to look at the butterfly curve for the feedback path of a latch, it has two stable points (vdd,0) and (0,vdd) and one metastable point close to (vdd/2, vdd/2) depending on how the latch is sized. When the latch closes before the internal nodes had a chance to reach from (vdd,0) to (0,vdd) or vice versa, you may be stuck in the middle (Vx, Vy). If this is very close to the metastable point, you will be stuck for a long time there before resolving to (0,vdd) or (vdd,0) which ever is closer. The farther away from the metastable point and closer to one of the stable points you are when the latch closed, the faster you will resolve to the closest stable point ( or the closest gate as in the above example).

my 2 cents

ASIC_intl

Joined: 18 Jan 2008
Posts: 199

13 Aug 2008 6:57 clock domain crossing coherent

Hi appalix

Why will not the coherency in the databit be acceptable?
There will be a metstable state of 0101 in your case. But after a latency you will get the correct state of 1111 which will be sampled to the new clock domain. What problem will this erroneous state of 0101 will create?

Now if 0101 crates a problem as a metastable state. Then for a single bit also the intermediate metastable single bit state will create the same problem.

Added after 3 minutes:

Hi apallix

Why will not the coherency in the databit be acceptable?
There will be a metstable state of 0101 in your case. But after a latency you will get the correct state of 1111 which will be sampled to the new clock domain. What problem will this erroneous state of 0101 will create?

Now if 0101 crates a problem as a metastable state. Then for a single bit also the intermediate metastable single bit state will create the same problem.

Added after 13 minutes:

HI kvingle

Where in wakerely they have described about synchronization of a data bus like 8 bit and 16 bit?

bibo1978

Joined: 01 May 2004
Posts: 229
Helped: 6

13 Aug 2008 8:42 metastable clock domain crossing

ASIC_int

0101 is not a metastable state, when you read 0101 usually means that data was read on its transition state but since you read some value then you read right the problem mainly is that value that you didn't reach metastable state.
If you read data bus async you may get fake value I.e value that is not what it is in its clock domain because simply a clock domain defines exactly when data must be read by the clock itself
That's why why u will need an Async FIFO to transmit data from one domain to the other
because from one side the FIFO is capable to read data right and from the other side it will deliver it right I.e it will simply hold data until it is valid to be read from the other side
for example imagine two two group of water people that are transferring balls between them on group is doing this with some defined timing such that anyone in this group will try to get the ball at some very small period of time if he rounds a ball then it is one else is zero each member of this group is authorized to prepare the passed ball to the next member in some definite time such that when the other member try to get the ball it is valid the other group is doing the same but with another rate now interfacing the two groups directly will be a mess we need some group in the middle that knows can get the balls from one clock and then send it to the other this group job is not easy they might need to hold the balls for some time until it is valid to be read on the other clock domain

ASIC_intl

Joined: 18 Jan 2008
Posts: 199

13 Aug 2008 10:40 convert signal from one clock domain to another

HI bibo1978

I understand what u have written. But instead of four bits if you have one bit then also you can have a metastable invalid bit when you are using two flop synchronizer instead of a FIFO. But for a single bit we do not go for a FIFO but go for a two flop synchronizer. How can you allow the illegal metastable one bit but you cannot allow illegal metastable multibit state (e.g. 0101 here)?

bibo1978

Joined: 01 May 2004
Posts: 229
Helped: 6

13 Aug 2008 15:52 how is appalix

1-synchronizer is used to decrease the probability of metastability not to allow it!
2-One bit is not data it is a signal if you want just sample it directly you will only have a more probability that ur circuit fail or hang or read wrong data for a longer period of time
you need to read more about the subject that's it I can't be more comprehensive sorry

ASIC_intl

Joined: 18 Jan 2008
Posts: 199

14 Aug 2008 5:54 clock domain crossing register fifo

Hi bibo

I have read it. Probably u need to either think of the matter more or read about more. I am sorry for this.

feel_on_on

Joined: 29 Apr 2005
Posts: 260
Helped: 1

18 Aug 2009 11:00 cross clock domain fifo grey code

I also have the same problem as ASIC_intl, I don't know if the problem have been solved ? Can ASIC_intl tell me ?

bibo1978

Joined: 01 May 2004
Posts: 229
Helped: 6

19 Aug 2009 6:47 crossing clock domains + digital design

Bottom line use Async FIFO

feel_on_on

Joined: 29 Apr 2005
Posts: 260
Helped: 1

20 Aug 2009 3:47 cross clock domain synchronization double flop

if you have one bit then also you can have a metastable invalid bit when you are using two flop synchronizer instead of a FIFO. But for a single bit we do not go for a FIFO but go for a two flop synchronizer. How can you allow the illegal metastable one bit but you cannot allow illegal metastable multibit state (e.g. 0101 here)?

bibo1978

Joined: 01 May 2004
Posts: 229
Helped: 6

20 Aug 2009 6:22 grey code in clock crossing domain

Guys,
if you read wrong data this doesn't mean metastability ... !
just simply according to any logic data should be sampled at some specific time (hold period) which is managed by passing the clock.
when you read data Bus Asynchronously you may get wrong value because you might be sampling the data on its transmittion period and there are many things that might cause wrong bus data output one of which is the wire delay is different, the Flip flop response time, clock jitter, recieving FF clock delay, sampling at invalid data value (between the logic zero and one) ... etc. The list is big here, so what you have to do is to avoid all of this one way or the other

I want to clarify metastability a bit here, it is a very small range of input that may cause circuit to hang i.e. transistor will be in active state.
just to get it more clear, a gate will definitely behave in specific manner if input voltage is within some range for example TTL will give you 0 if input is between 0-0.2 Volt. and one if input is between 3.7 and 5 (this values might be wrong values I am using it for clarification only you can search the net to get the range of TTL logic for input and output) if the data input value is between 0.2 - 3.7 the output might be 0-1 (can not determine), there is within this range avery small range that will make the circuit go to metastability (i.e. transistors will be in active state and transmit this to next output). this (range) is very small and actually is not precise because it depends on the dopping, the material type, temprature ... etc. so simply there is just a very small change that if you sample the data you might sample it with this value that might cause a circuit failure or a hang period for transistor to return from active state .. it might cause also total circuit failure ! very rarely if it propagates.
This is metastability Guys this is metastability .. nothin else.
so as long as your circuit is behaving right which means that it is working then you didn't get to metastability state.
I hope it is clear now.
Now back to our discussion you will still need a Async FIFO for Data bus and in case of one signal you might use only two FF in case you are sampling at a higher speed, you will need other techniques in case you are sampling a a lower clock speed.
hope this help

feel_on_on

Joined: 29 Apr 2005
Posts: 260
Helped: 1

20 Aug 2009 10:58 8 to 16 cross clock

You mean that metastability with two DFF still is possible to cause a circuit failure ,only beacuse the range is small .When transmit a "1" to 2 DFF from a clock domain to another clock domain, Due to setup timing , circuit enter into metastability in the first DFF ,although in the seconde DFF , the data have been stable ,but now it is "0". this cause a failure.

bibo1978

Joined: 01 May 2004
Posts: 229
Helped: 6

20 Aug 2009 11:57 how does grey code help async clock crossing

I don't understand your question however I will add a note, that might answer u, the metastability filter (two FFs usually) diminish the probability of metastability propagation, which might cause circuit failure, metastability might also cause circuit to hang .. unexpected behavior generally , more FFs will decrease metastability exponentially.. yet there are no way to have a zero propability for metastability propagation (in Async. circuits or in life) but it can be very low such that it "may" never occur during lifetime of the circuit.
Two FF difinitely will make this happen three is a plus.

feel_on_on

Joined: 29 Apr 2005
Posts: 260
Helped: 1

20 Aug 2009 15:57 data bus clock domain crossing

more FFs will decrease metastability, but are you sure the correct data you got ? If you transmit a "1",but you get a "0" in the end . more FFs only can solve metastability ,but can't sure a correct data you get . ie: now transmit "1" through one FF crossing clock domain ,you get a metastability. For solving the metastability ,you add another FF,now two FFs. although you solved metastability,but you maybe get a "0" in the two FFs output.

feel_on_on

Joined: 29 Apr 2005
Posts: 260
Helped: 1

21 Aug 2009 4:10 clock domain crossing synchronizer

hi,bibo1978
Can you help me ? I don't understand why the deepth is 20bit . thanks a lot .

the spec as following :

The REF_CLK frequency shall be 50Mhz+/-50ppm with a duty cycle between35% and 65% . the recovered clock is 25Mhz+/-100ppm.

While the PHY may recover clock from in the incoming data stream,the receiver shall account for the differences between the local REF_CLK and the recovered clock through use of sufficient elasticity buffering. The elasticity buffer design shall not affect the Inter-Packet Gap for received IPGs of 36 bits or greater. To tolerate the clock variations specified here for Ethernet MTUs,the elasticity buffer shall tolerate a minimum of +/-10 bits. This implies that the FIFO is at least 20bits deep and doesnot transfer recovered data on RXD[1:0] unitil FIFO is half full.

anyone can tell me how to got +/-10bit