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dinesh.4126
Joined: 27 Feb 2008
Posts: 35
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 24 Jul 2008 16:43 Delay Concept |
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Hi,
As we know that in verilog or VHDL delay are non syntesiable only they we use in writting the test bench ,so if want to use delay in our design then how we can use
it.
THANX.
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mouzid
Joined: 22 Jun 2007
Posts: 205
Helped: 10
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| 24 Jul 2008 16:48 Re: Delay Concept |
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| dinesh.4126 wrote: |
Hi,
As we know that in verilog or VHDL delay are non syntesiable only they we use in writting the test bench ,so if want to use delay in our design then how we can use
it.
THANX. |
Buffer insertion introduces delays.
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kokabanga
Joined: 02 May 2005
Posts: 45
Helped: 4
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| 24 Jul 2008 17:01 Re: Delay Concept |
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| dinesh.4126 wrote: |
Hi,
As we know that in verilog or VHDL delay are non syntesiable only they we use in writting the test bench ,so if want to use delay in our design then how we can use
it.
THANX. |
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saikat
Joined: 21 Oct 2005
Posts: 46
Helped: 4
Location: mumbai
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| 25 Jul 2008 10:06 Re: Delay Concept |
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Use a simple counter (std_logic_vector) to count clock edges. First calculate the time period of a clock cycle and how much delay you require. From this data, you can calculate how many number of clock edges (either positive or negetive, but not both) you need to wait (or count) for providing the required time delay.
implement the same in a process block.
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avimit
Joined: 16 Nov 2005
Posts: 415
Helped: 68
Location: Fleet, UK
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| 31 Jul 2008 11:37 Delay Concept |
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Well, it depends how much delay you would like. In a synthesizeable design its not possible to have a definite delay inserted when the delay value is less than 1/2 the clock period of the clock you are using. Using buffers will give you a delay, but the delay value will not be deterministic. Well, if you would like to have a delay of more than 1/2 a clock period, then you can use a counter to implement that, or if the delay is just 1 or 2 clock periods, then just pass the signal throuth 1 or 2 D flip flops respectively. Hope it helps,
kr,
Avi
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