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Message |
pwq1999
Joined: 02 Mar 2008
Posts: 39
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 23 Jul 2008 11:44 synchronous reset (verilog) |
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i write synchronous reset as follow:
always@(posedge sys_clk_25m)
begin
if(!syn_rst_n)
toggle_bit<=1'b0;
else
begin
if(!rtl8305_mtxen)
toggle_bit<=1'b0;
else
toggle_bit<=~toggle_bit;
end
end
but when i view the RTL Schematic, i found that the syn_rst_n signal make the logic or with the !rtl8305_mtxen signal ,which i don't expecte, so anyone can help me out how to express the synchronous reset without adding additional logic in reset input?
thanks in advance!
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j_andr
Joined: 31 Mar 2008
Posts: 80
Helped: 13
Location: europe
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| 23 Jul 2008 12:41 Re: synchronous reset (verilog) |
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| pwq1999 wrote: |
/.../ found that the syn_rst_n signal make the logic or
with the !rtl8305_mtxen signal/... |
this is what you wrote in the rtl;
can you describe the functionality you need ?
--
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pwq1999
Joined: 02 Mar 2008
Posts: 39
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| 23 Jul 2008 14:27 synchronous reset (verilog) |
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| i want a multiplexer appear in front of the flip-flop, and the rtl8305_mtxen behaves as the select control signal. actually i don't want any logic appear in the reset input of the flip-flop, as i worry that it may make glitch in the reset input of flip-flop.
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research_vlsi
Joined: 15 Nov 2006
Posts: 84
Helped: 3
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| 23 Jul 2008 15:20 Re: synchronous reset (verilog) |
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u can try your code like this
| Code: |
wire out;
always@(posedge sys_clk_25m)
begin
if(!syn_rst_n)
toggle_bit<=1'b0;
else
toggle_bit<=out;
/*if(!rtl8305_mtxen)
toggle_bit<=1'b0;
else
toggle_bit<=~toggle_bit;*/
end
assign out = rtl8305_mtxen?!toggle_bit:1'b0; |
so that u will not get any logic in reset of your flip flop. since u used !syn_rst_n, so inverter will be inferred in synthesis tool..
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j_andr
Joined: 31 Mar 2008
Posts: 80
Helped: 13
Location: europe
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| 23 Jul 2008 15:50 Re: synchronous reset (verilog) |
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| pwq1999 wrote: |
| want a multiplexer appear in front of the flip-flop |
in fact a mux is also a set of and/or gates, or - going down
to fpga architecture - it is composed of look-up tables as AND/OR gates are;
mux/or/and - it's just a graphical representation of the rtl;
| Quote: |
| i worry that it may make glitch in the reset input of flip-flop |
you can have the same glitches if a mux is used;
but any glitches, if out of clock active slope, are not danger if they
appear at the input of a flip-flop;
--
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pwq1999
Joined: 02 Mar 2008
Posts: 39
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| 24 Jul 2008 2:29 synchronous reset (verilog) |
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| thanks ,j_andr and research_vlsi, you two help me out! now i get the idea!
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xihushui
Joined: 12 May 2006
Posts: 53
Helped: 1
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| 24 Jul 2008 16:09 synchronous reset (verilog) |
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try this code
always@(posedge sys_clk_25m)
begin
if(!syn_rst_n) begin
toggle_bit<=1'b0;
end
else if(!rtl8305_mtxen) begin
toggle_bit<=1'b0;
end
else begin
toggle_bit<=~toggle_bit;
end
end
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pwq1999
Joined: 02 Mar 2008
Posts: 39
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| 25 Jul 2008 14:02 synchronous reset (verilog) |
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| i can not see your code have difference with the code i posted above!
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sheik_vb
Joined: 21 Jul 2006
Posts: 54
Helped: 3
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| 26 Jul 2008 11:45 Re: synchronous reset (verilog) |
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try this code
assign reset_n = syn_rst_n & rtl8305_mtxen ;
always@(posedge sys_clk_25m)
begin
if(!reset_n) begin
toggle_bit<=1'b0;
end
else
toggle_bit<=~toggle_bit;
end
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kib
Joined: 27 Mar 2003
Posts: 120
Helped: 7
Location: Bangalore, India
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| 26 Jul 2008 13:30 Re: synchronous reset (verilog) |
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try this code
| Code: |
assign temp = rtl8305_mtxen ? (~toggle_bit) : 1'b0;
always @(posedge sys_clk_25m)
begin
if(!syn_rst_n)
toggle_bit <= 1'b0;
else
begin
toggle_bit <= temp;
end
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pwq1999
Joined: 02 Mar 2008
Posts: 39
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| 27 Jul 2008 14:27 synchronous reset (verilog) |
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| thanks you all, i have change the synchronous reset to asynchronous reset, and no logic appear in front of the reset of the flip-flop,but i believe that kib's code works well, and thanks you all again!
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