skycanny
Joined: 23 Dec 2004
Posts: 30
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 23 Jul 2008 10:11 safe state machine problem |
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Hi all guys:
I want ro generate a safe state machine, When the machine enter an unexpected state or an unreachable state, it can recove from these error state and run continuely. I have created a finite state machine by VHDL, synthesized by synplify with the atrribute "safe", however, the log warns that "OTHERS clause is not synthesized", and the synthesed result is tha same as the one sythsized without the attribute "safe". Whenever I add the attribute "safe" in the *.sdc file or directly in the VHDL source file, syplify shows the warning mentioned above. I refer http://www.synplicity.com/university/pdfs/designing_safe_vhdl.pdf as my guide, but get this result.
what is wrong? how can I get a safe state machine synthesized by synplify?
Best regard.
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FvM
Joined: 22 Jan 2008
Posts: 2240
Helped: 374
Location: Bochum, Germany
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| 23 Jul 2008 10:48 Re: safe state machine problem |
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| The safe behaviour is not necessarily corresponding to the existence of an OTHERS state to my opinion. When the OTHERS state is recognized as unreachable by the FSM compiler, it's probably eliminated as with any other FSM style. But due to the safe opion, transitions from illegal states to the reset state should be implemented. You can try by simulation.
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