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Black Jack
Joined: 02 Dec 2003
Posts: 214
Helped: 10
Location: UKRAINE
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 15 Jul 2008 13:07 Simulation with VHDL: How to create stimulus with Jitter? |
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Hello!
I`m need to create clock stimulus with jitter.
I think that need to generate random numbers in desired range and
add/substract from constant for period.
What you think about this?
Can anyone share examples of VHDL code?
-- Regards, Jack
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nand_gates
Joined: 19 Jul 2004
Posts: 898
Helped: 117
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| 16 Jul 2008 10:15 Re: Simulation with VHDL: How to create stimulus with Jitter |
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| You are on right track! That the way we generate clock with gitter!
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mehrzad321
Joined: 14 Feb 2008
Posts: 5
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| 23 Jul 2008 8:26 Simulation with VHDL: How to create stimulus with Jitter? |
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| You must use functions in "ieee.math_real" library to generate random numbers in a limited interval.
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Black Jack
Joined: 02 Dec 2003
Posts: 214
Helped: 10
Location: UKRAINE
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| 23 Jul 2008 8:36 Re: Simulation with VHDL: How to create stimulus with Jitter |
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| tohidsedghi wrote: |
| it is perfect |
1) Whats "perfect"? 
2) Thanks for gurus from http://verificationguild.com.
They advise me with code like this
| Code: |
sys_clk_process: process
-- variables for uniform
variable seed1, seed2 : positive;
variable r : real;
begin
uniform(seed1, seed2, r);
d <= r * 1 ns;
wait for SYS_CLK_PERIOD/2;
clock <= '0';
wait for SYS_CLK_PERIOD/2;
clock <= '1';
end process;
sys_clk <= transport clock after d;
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