BlackOps
Joined: 02 Jan 2005
Posts: 260
Helped: 9
Location: AZERBAIJAN
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 09 Jul 2008 16:50 Convert IF-THEN-ELSE statements to the STATE MACHINE |
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Hello, i have a piece of VHDL code which is working good, and performs what i want. But now, i would like to convert it to FSM.. so that it will act not just like if-then-else VHDL code, but as the state machine.
here is the code which i have now:
| Code: |
-- HORIZONTAL_FSM: PROCESS(Clock)
-- BEGIN
--
-- IF (Clock'EVENT AND Clock = '1') THEN
--
-- -- count begins from HACTIVE region.
--
--
--
-- IF (HCounter = HACTIVE) THEN
-- hdata_on <= '0';
-- end if;
--
-- IF (HCounter = HACTIVE+HFP) THEN
-- hsync_on <= '0';
-- END IF;
--
-- IF (HCounter = HACTIVE+HFP+HSYNCH) THEN
-- hsync_on <= '1';
-- END IF;
-- IF (HCounter = HACTIVE+HFP+HSYNCH+HBP) THEN -- If HCounter reaches the value 1344:
-- hdata_on <= '1'; -- Turn on active video again,
-- HCounter <= (OTHERS => '0'); -- Reset HCounter to 0,
-- NextLine <= '1'; -- and set NextLine signal to HIGH.
-- ELSE
-- HCounter <= HCounter + 1; -- otherwise, increment HCounter on every
-- NextLine <= '0'; -- active edge of the Clock signal.
-- END IF; -- and keep NextLine signal LOW
--
-- END IF;
--
-- END PROCESS;
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i have converted it to the state machine code, and decided to start count from HSYNCH instead of HACTIVE, here is my code:
| Code: |
CONSTANT HSYNCHc: INTEGER := 136; -- Horizontal synchronization
CONSTANT HBPc: INTEGER := 160; -- Horizontal back porch
CONSTANT HACTIVEc: INTEGER := 1023; -- 1024 active video data (count begins from 0)
CONSTANT HFPc: INTEGER := 24; -- Horizontal front porch
-- Total number of clocks is 1344
type HSTATE is (HSYNCH,HBP,HACTIVE,HFP);
type VSTATE is (VSYNCH,VBP,VACTIVE,VFP);
signal horstate: HSTATE;
signal hornstate: HSTATE;
SIGNAL HCounter: STD_LOGIC_VECTOR(10 DOWNTO 0) := "00000000000";
-- HORIZONTAL FSM
horizontal_state: process(Clock,reset) -- > horizontal FSM control state machine
begin -- this state machine has FOUR states.
if(reset='0') then -- initial state is HSYNCH.
horstate <= HSYNCH; -- transition from one state to another occurs
elsif (rising_edge(Clock)) then -- every Clock clock signal?
horstate <= hornstate;
end if;
end process;
horizontal_nextstate: process(horstate)
begin
hornstate <= HSYNCH;
hdata_on <= '0';
hsync_on <= '0';
NextLine <= '0';
case horstate is
when HSYNCH =>
if (HCounter = HSYNCHc) then
hdata_on <= '0';
hsync_on <= '1';
hornstate <= HBP;
else
hornstate <= HSYNCH;
end if;
when HBP =>
if (HCounter = HSYNCHc + HBPc) then
hdata_on <= '1';
hsync_on <= '1';
hornstate <= HACTIVE;
else
hornstate <= HBP;
end if;
when HACTIVE =>
if (HCounter = HSYNCHc + HBPc + HACTIVEc) then
hdata_on <= '0';
hsync_on <= '1';
hornstate <= HFP;
else
hornstate <= HACTIVE;
end if;
when HFP =>
if (HCounter = HSYNCHc + HBPc+ HACTIVEc + HFPc) then
hdata_on <= '0';
hsync_on <= '0';
hornstate <= HSYNCH;
NextLine <= '1';
HCounter <= (OTHERS => '0');
else
hornstate <= HFP;
end if;
end case;
end process;
horizontal_fsm: process(Clock)
begin
if (rising_edge(Clock)) then
HCounter <= HCounter + 1;
end if;
end process;
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problem is... my HCounter signal is not incrementing... it is just stays in an undefined X value, when i try this code in Modelsim...
could u show me my error please?
thanks
Added after 4 hours 14 minutes:
well....as always the best place to get answer to your problem is to read book again and rebuild your problem basing on the examples inside the book.
here is the FSM model behavioral code for the if-then-else code above.
| Code: |
horizontal_next_state_logic: process (Clock, reset)
begin
if (reset = '1') then
horstate <= HSYNCH;
elsif (Clock'EVENT AND Clock = '1') then
case horstate is
when HSYNCH =>
if (HCounter = HSYNCHc) then
horstate <= HBP;
else
horstate <= HSYNCH;
end if;
when HBP =>
if (HCounter = HSYNCHc + HBPc) then
horstate <= HACTIVE;
else
horstate <= HBP;
end if;
when HACTIVE =>
if (HCounter = HSYNCHc + HBPc + HACTIVEc) then
horstate <= HFP;
else
horstate <= HACTIVE;
end if;
when HFP =>
if (HCounter = HSYNCHc + HBPc + HACTIVEc + HFPc) then
horstate <= HSYNCH;
else
horstate <= HFP;
end if;
end case;
if (HCounter = HSYNCHc + HBPc + HACTIVEc + HFPc) then
HCounter <= (OTHERS => '0');
NextLine <= '1';
else
HCounter <= HCounter + 1;
NextLine <= '0';
end if;
end if;
end process;
horizontal_output_logic: process (horstate)
begin
case horstate is
when HSYNCH =>
hdata_on <= '0';
hsync_on <= '0';
when HBP =>
hdata_on <= '0';
hsync_on <= '1';
when HACTIVE =>
hdata_on <= '1';
hsync_on <= '1';
when HFP =>
hdata_on <= '0';
hsync_on <= '1';
end case;
end process; |
Last edited by BlackOps on 31 Jul 2008 11:13; edited 1 time in total |
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tkbits
Joined: 04 Dec 2004
Posts: 215
Helped: 30
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| 13 Jul 2008 19:27 Re: Convert IF-THEN-ELSE statements to the STATE MACHINE |
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You're trying to reset the counter directly in state HFP.
Do it by creating a reset signal, and use the reset signal in the counter process to reset the counter. Set the state of the reset signal just like the output signals in the SM. Activate the reset when needed, and ensure it's inactive when it's not needed.
The reset can be asynchronous or synchronous.
1) An asynchronous reset will go active in the state you activate it.
2) If you do a synchronous reset, the reset signal needs to go active in all immediately preceding states.
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BlackOps
Joined: 02 Jan 2005
Posts: 260
Helped: 9
Location: AZERBAIJAN
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| 15 Jul 2008 11:32 Convert IF-THEN-ELSE statements to the STATE MACHINE |
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| yes i agree with u mostly, thanks anyway for information, but my initial state is HSYNCH, and i dont try to reset it to HFP, but the reset function may be implemented here as u say.
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