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Equivalence

 
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mouzid



Joined: 22 Jun 2007
Posts: 202
Helped: 10
Post09 Jul 2008 10:26   Equivalence
Hello,
Please see the figure below.
Are these two circuits equivalents?
Which one is better ? Why ?

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AdvaRes



Joined: 14 Feb 2008
Posts: 603
Helped: 33
Post09 Jul 2008 10:35   Equivalence
Hi,
The second one coz its layout is smaller if compared to the second.
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needforspeed



Joined: 21 Dec 2005
Posts: 22
Helped: 1
Location: FRANCE
Post09 Jul 2008 11:54   Equivalence
it's dependent on your application and layout. If you want good matching of DFFs, I think the second one is better. in the first scheme, two input of DFF may show some difference as the mismatching of the INVs.
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Paramjyothi



Joined: 09 Jul 2008
Posts: 30
Helped: 4
Post09 Jul 2008 12:05   Re: Equivalence
Your schematics are incomplete as to say which one is better. Whenever flipflops comes into picture clock comes into account. Clock routing or simulations are most critical regarding matching parasitics in layout designing or balancing the skew for PNR blocks.

If the output of the inverters/buffers are going to the CLK pin of the flipflop then 1st schematic should be considered as it serves the purpose for both layout designing & PNR block. But if the output is going to any pin then 2nd schematic is better as it saves area for layout designing and for PNR block it reduces additional net delays & net routings.
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mouzid



Joined: 22 Jun 2007
Posts: 202
Helped: 10
Post09 Jul 2008 13:19   Re: Equivalence
Paramjyothi wrote:
Your schematics are incomplete as to say which one is better. Whenever flipflops comes into picture clock comes into account. Clock routing or simulations are most critical regarding matching parasitics in layout designing or balancing the skew for PNR blocks.

If the output of the inverters/buffers are going to the CLK pin of the flipflop then 1st schematic should be considered as it serves the purpose for both layout designing & PNR block. But if the output is going to any pin then 2nd schematic is better as it saves area for layout designing and for PNR block it reduces additional net delays & net routings.


I'm talking in general. I wanna know the difference between the 2 circuits in terms of area, delays, skew, input capacitances, layout etc when the output of inverter are going to DFF clock pins or when they goes to anoher pins.
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