How to view synthesis results in Xilins ISE

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elec-eng

Joined: 16 Nov 2006
Posts: 277
Helped: 15

08 Jul 2008 17:24 ise synthesis report

hi

I use Xilins ISE 10.1 and I can ge thrTL view
Now I want to view the final results of the synthesis process in a graphical form (i.e. gates , multiplexers,....and their inter-connections afer optimization) in order to be able to know the quality of the synthesis process

so please tell me how to do a thing like this

nitu

Joined: 05 Dec 2004
Posts: 96
Helped: 3

08 Jul 2008 19:37 ise view ngc

Hi..

In ISE 9.2 you can see the utilization of LUTs and slices in the Synthesis report. I am not sure whether the same is there in ISE 10.1.

Also, you need to change the properties of synthesis after right clicking on the synthesis in the process window. Now with different properties run the synthesis and then make comparitive matrix with these results.

I hope this helps.

echo47

Joined: 07 Apr 2002
Posts: 4206
Helped: 566

08 Jul 2008 21:52 ise view critical path

You can view a schematic representation of your NGC file with Project Navigator. Click File, Open (not Open Project), and then pick your NGC file. It's a sprawling multi-page view. This view hasn't been very helpful to me.

You can also view the fully routed device in FPGA Editor. It lets you zoom in to see component placement, route paths, and internal configuration of slices and IOBs. It may be more detail than you need. You can even edit things, if you are daring.

pini_1

Joined: 18 Jun 2007
Posts: 288
Helped: 17

09 Jul 2008 4:41 xilinx multipage schematic

Best way is to go over the report that the tool creates.
Here is an example

http://bknpk.no-ip.biz/usb_8051_verilog_syn/usb_1_syn_intro.html
http://bknpk.no-ip.biz/usb_8051_verilog_syn/usb_verilog_syn_flow.pdf

deepu_s_s

Joined: 24 Mar 2007
Posts: 329
Helped: 13

09 Jul 2008 5:11 view ngc files

I think ur asking about the RTL schematic representation or the log file?

If that is for the RTL schematic, then u
1)go to VIEW.

2)check whether the process is checked or not. If not , then click on that process.

3) Then u can see a new process window on the down left of the screen.

4)In that u got SYNTHESIS - XST

5) U will find VIEW RTL SCHEMATIC.click on that.

6) A new window will open with the top module, then right click on that and click on push into the schematic.

7) Then u can see th sub-blocks or interconnections of the gates and others etc..

Cool

This would be ur schematic representation of ur netlist

I hope this helps u..

Bye
Deepak

victoria_jitesh

Joined: 27 Nov 2006
Posts: 49
Helped: 1

09 Jul 2008 13:38 view synthesis report

This are possible solution for query u asked (if your synthesis tool is Xilinx Project Navigator):
1.View Technlogy schematic file :This file will show how logic gates and other comb ckt is mapped in terms of LUT in FPGA. Double click on any LUT ,there u will see the internal schematic diagram and its truth table and K map.

2.After synthesis open generate place and route option and in that open "edit and place (floorplanner)option.This will open two window viz one floorplan editor and other placement window in which click on any device ,it will show fly(connectivity)lines that will show connection of that component w.r.t other component.
Now at this point ,if u want to further optimise any critical path in your design use floorplan editor.

If this clear ur doubts ,please don't forget to place help button.[/img]

haneet

Joined: 07 Nov 2006
Posts: 149
Helped: 15

09 Jul 2008 20:44 how view result of synthesize xilinx

hi frndz...

can you tell me how can i edit the clock frequency for synthesis.
In general the Xilinx synthesis is done using the default clock i.e 'pclk'
how can i change the values of 'pclk'??

thanks,

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sandeep_sggs

Joined: 21 Jan 2008
Posts: 120
Helped: 3

06 Aug 2008 8:17 xilinx synthesis report options ise

Hi all,
ui have used ISE9.1....anyways 10.1 will not be much different....
In order to view the utilization of LUTs and other resources, should see the synthesis report..and the floor plan..still u can get the report after every process: eg TRANSLATE,MAP,PAR(place and route) if you want.......
i think i m clear...................