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ASIC_intl
Joined: 18 Jan 2008
Posts: 199
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 08 Jul 2008 13:36 counter design with negative and positive edge |
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HI
I want to know the way of designing a counter using both the positive and negative edgse of the clock to get output waveforms which are not of 50% duty cycle.
Regards
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gliss
Joined: 22 Apr 2005
Posts: 670
Helped: 61
Location: Boston
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08 Jul 2008 20:10 counter design with negative and positive edge |
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| You can try inserting buffers to get the output data away from the clock.
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kumarghz
Joined: 25 Nov 2006
Posts: 48
Helped: 3
Location: Penang, malaysia
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20 Jul 2008 16:32 Re: counter design with negative and positive edge |
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| can you further describe about wht design you want?
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sree205
Joined: 13 Mar 2006
Posts: 421
Helped: 30
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21 Jul 2008 7:15 counter design with negative and positive edge |
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how about this following code? does this meet ur spec. ?
`define width 2
`define delay 2
module example(clk,rst,counter);
input clk,rst;
output [`width:0] counter;
reg [`width:0] counter;
always@(clk)
gen_clk = #`delay clk;
always@(posedge clk or negedge gen_clk or negedge rst)
if(!rst)
counter <= 'b0;
else
counter <= counter+1'b1;
endmodule
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FvM
Joined: 22 Jan 2008
Posts: 5160
Helped: 767
Location: Bochum, Germany
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21 Jul 2008 7:31 Re: counter design with negative and positive edge |
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The suggested code isn't synthesizable cause it would require flip-flops that operate on both edges. They don't exist in FPGA or ASICs as far as I know. Also delay statements are usable in simulation only!
Various solutions for frequency dividers operating on both edges have been posted at EDAboard, I assume that you'll be able to find some of them, They are generally using positive and negative clocked flip-flops with combinational logic.
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sree205
Joined: 13 Mar 2006
Posts: 421
Helped: 30
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21 Jul 2008 7:41 counter design with negative and positive edge |
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| yes, its not a synthesizable option. it can only be used in behavioural modelling.
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21 Jul 2008 7:41 Ads |
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ASIC_intl
Joined: 18 Jan 2008
Posts: 199
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21 Jul 2008 9:03 Re: counter design with negative and positive edge |
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Hi FVM
Can u please let me know some websites in Edaboard or any other websites where I can find out solutions of frequency dividers operating in both the edges?
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