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tromeros
Joined: 27 Nov 2003
Posts: 38
Helped: 2
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 02 Jul 2008 14:02 Virtuoso hierarchical layout design |
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Hi to all! I have the following problem.
I made a layout component in Virtuoso that is simply a stack of metals with vias between them.
When I use this component in my main layout design in order to connect two metals the connectivity checker shows that they are not connected.
Is there something I am missing?
Thanks in advance.
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microchaos
Joined: 10 Dec 2003
Posts: 24
Location: Lithuania
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| 02 Jul 2008 14:10 Virtuoso hierarchical layout design |
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| I think the pins are missing?
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k_90
Joined: 25 Jan 2006
Posts: 104
Helped: 14
Location: Scotland,GB
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| 02 Jul 2008 14:36 Re: Virtuoso hierarchical layout design |
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are you using virtuoso XL?
if so you need to use the correct pcell and without hierarchy when connecting.
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kumar_eee
Joined: 22 Sep 2004
Posts: 369
Helped: 7
Location: India
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| 03 Jul 2008 17:45 Re: Virtuoso hierarchical layout design |
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| I agree with K_90, If u are using VXL, then check for correct PCell. Otherwise you will get Error.
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tiger888
Joined: 25 Apr 2008
Posts: 11
Helped: 2
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| 06 Jul 2008 5:20 Re: Virtuoso hierarchical layout design |
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Try the "mark" net command in VXL or Virtuoso Turbo.
If it does not work, you'd better check your techfile if the via layer definitions been added.
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k_90
Joined: 25 Jan 2006
Posts: 104
Helped: 14
Location: Scotland,GB
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| 09 Jul 2008 9:14 Re: Virtuoso hierarchical layout design |
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| Mark net does exactly what it says on the tin, it marks the net nothing more. To keep connectivity you need to drop a via/contact down from the primatives/cadence library one at a time.
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