ktsangop
Joined: 02 Apr 2008
Posts: 15
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 30 Jun 2008 23:15 Verilog module hierarchy causing problems |
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Hi there!
I have a question regarding verilog.
I have a very simple shift register like code like this :
| Code: |
module eleos_sub(NOCclk,in2,full3);
input NOCclk,in2;
output full3;
reg [7:0] mem=8'b0;
reg full3reg;
assign full3=full3reg;
always @ (posedge NOCclk)
begin
if (mem[7]!=1'b1)
begin
mem=mem<<1;
mem[0]=in2;
end
else if (mem[7]==1'b1) full3reg=1'b1;
end
endmodule |
Input is serial (10101010) and as the first input is always 1, it is full when mem[7] = 1.
When it's full the full output is set to 1. This works fine on its own. (cool.jpg)
BUT...when i put this code inside another module (top) things get weird.
This is the top module :
| Code: |
module eleos (NOCclk,sin,full);
input NOCclk,sin; output full; wire in1,full2; reg in1_reg;
assign in1=in1_reg;
assign full=full2;
eleos_sub ss2 (NOCclk,in1,full2);
always @ (posedge NOCclk)
begin
in1_reg=sin;
end
endmodule |
I just want to pass the value of sin to the first module as input and get the full signal output.
The serial input bits are 10101010. But the first value that gets into the mem register is x. (notcool.jpg)
It's very strange ...or i am missing something really fundamental.
Please take a look at the pics and help me if you can.
Thanks in advance!!!
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