linan0827
Joined: 22 Oct 2007
Posts: 4
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 28 Jun 2008 12:21 How to embed a VHDL entity to an analog simulator? |
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Hello everyone!
I am now designing a successive approximation ADC as a final project. As you know this kind of ADC need a digital circuit as a controller to control some switches connected to the capacitors array. Now the situation is I dont need to implement this controller in transistor level. So I want to write a VHDL code to describe the function of it.
As far as I know, VHDL-AMS or Verilog-AMS could describe an analog circuit in a VHDL or Verilog codes. However, my question is something in reverse direction: how should I compile the VHDL code and integrate it with my other analog components and how should I design the interface in between the digital and analog world, like defining "1" to Vdd and "0" to gnd?
I am now using cadence enviroment and spectre as my analog simulator. Could anyone give some help? Thank your very very very much in advance!!!!!!
Li Nan
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