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ASIC_intl



Joined: 18 Jan 2008
Posts: 89
Post25 Jun 2008 8:27   dc DRC
Hi

In design compiler I found after synthesisi the timing is met but the DRC s (max_transition, max_capacitance) are being violated for some of the nets. Why are there DRC violation.

Regards.
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gliss



Joined: 23 Apr 2005
Posts: 669
Helped: 60
Location: Boston Metro Area
Post25 Jun 2008 22:41   dc DRC
You probably need to add constraints to your design so Design Compiler will synthesize around them and produce a DRC clean netlist.
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