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rinaishlene
Joined: 29 Nov 2005
Posts: 28
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 24 Jun 2008 6:04 Scan D Flip Flop |
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Hi
I'm designing a scan D Flip Flop by schematics.The problem is when I simulated the design,the output obtained is delayed by one clock cycle.I'm using Cadence IC Design tool to design the flip flop and using HSPICE to simulate the design.
Is the delay occur because of the design (from the schematic drawn),or from the setup and hold time or any other settting that must be taking place when using HSPICE to simulate the design.
If the delay occur because of the schematics design,would it be better to redesign the schematics by applying Kmap to further simplify the design or redesign the schematics by calculating its logical effort?
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ds18s20
Joined: 14 Jun 2006
Posts: 144
Helped: 2
Location: Bay Area
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| 26 Jun 2008 16:41 Re: Scan D Flip Flop |
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| rinaishlene wrote: |
Hi
I'm designing a scan D Flip Flop by schematics.The problem is when I simulated the design,the output obtained is delayed by one clock cycle.I'm using Cadence IC Design tool to design the flip flop and using HSPICE to simulate the design.
Is the delay occur because of the design (from the schematic drawn),or from the setup and hold time or any other settting that must be taking place when using HSPICE to simulate the design.
If the delay occur because of the schematics design,would it be better to redesign the schematics by applying Kmap to further simplify the design or redesign the schematics by calculating its logical effort? |
Post your rtl and will see 
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gliss
Joined: 23 Apr 2005
Posts: 675
Helped: 60
Location: Boston Metro Area
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| 26 Jun 2008 22:07 Scan D Flip Flop |
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If I understand the post, he didn't care RTL, just the schematics.
Post your schematic.
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rinaishlene
Joined: 29 Nov 2005
Posts: 28
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| 27 Jun 2008 8:48 Re: Scan D Flip Flop |
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Below is the image of the schematics
Added after 2 hours 51 minutes:
Here is the waveform generated for the scan flip flop
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nand_gates
Joined: 19 Jul 2004
Posts: 898
Helped: 117
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| 27 Jun 2008 11:38 Re: Scan D Flip Flop |
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It looks perfectly OK! While applying inputs w.r.t. clk you have not given any setup time.
Change ur inputs when the clock transitions from high to low and see the results.
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rinaishlene
Joined: 29 Nov 2005
Posts: 28
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| 01 Jul 2008 9:11 Re: Scan D Flip Flop |
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OK...but I don't think it follows the truth table
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