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ATPG timing problem

 
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binbin1994



Joined: 16 Jun 2008
Posts: 4
Post23 Jun 2008 7:57   ATPG timing problem
does it need to be de-skew for scan_en and test_clock?

how much the input_delay need to be set for scan_en signal in STA? assume 10MHz test cycle and 100MHz(max frequency) ATE.

thanks!
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leeguoxian



Joined: 20 Jun 2006
Posts: 54
Post27 Jun 2008 10:34   ATPG timing problem
just make sure there isn't any time violation.
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