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sandeep_sggs
Joined: 21 Jan 2008
Posts: 120
Helped: 3
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 21 Jun 2008 10:27 xilinx place and route |
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Dear all,
Can anybody tell me what is the significance of Manual "place and route" in Xilinx tools ( i Use xilinx9.1) and how to do it in DETAIL! Is manual process really useful considering the Good place and route algorithms embedded in vendor`s tools. i may be wrong, so please rectify me if so is the case!
Any good document for this subject is welcome. plz make it as early as possible..
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pini_1
Joined: 18 Jun 2007
Posts: 288
Helped: 17
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22 Jun 2008 14:34 place and route xilinx |
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Sometimes when your design reaches high utilization, the tool may have difficulties in the place and route process. So some help from the designer is required.
At least two approaches exist. One option is to manually do the entire problematic code. If the code is too large, this approach may be time consuming in debugging and maintaining.
Another approach might be to just slightly help the tool. Here is an example from a former design of mine using XILINX with 96% utilization.
1. Manually locate the FF devices of the main sequencer in the middle.
2. Force all slow logic like LED logic to be at the side (far away from downtown).
3. Try a few seeds and see the assorted results.
VHDL/VERILOG/XILINX backend examples at http://bknpk.no-ip.biz/
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farhantariq
Joined: 13 Jun 2006
Posts: 62
Helped: 2
Location: Pakistan
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23 Jun 2008 14:04 manual place and route |
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| Well dear The scene is just that the Vendor toll is a General tool.ya thats what professional but Designer Interaction Make it more Specific and effecient.
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sanjay11
Joined: 07 Dec 2006
Posts: 32
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27 Jun 2008 7:00 place and route |
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it always helps if at least the design blocks are placed manually (near to their respective IO's).
It reduces the burden on the tool to a large extent and achieve better timing.
Not each and every signal and module needs to be manually handled. A top level manual placement of blocks (guided place and route) result in less run time too.
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victoria_jitesh
Joined: 27 Nov 2006
Posts: 49
Helped: 1
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27 Jun 2008 15:00 how to do place and route in xilinx |
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SOME DO'S AND DON'Ts TO BE CONSIDER WHILE PLACE AND ROUTE
Flip- flops are almost free in FPGAs
In FPGAs, the area consumed by a design is usually determined by the amount of combinational circuitry, not by the number of ip- ops.
Aim for using 80–90% of the cells on a chip.
If you use more than 90% of the cells on a chip, then the place-and-route program might not be able to route the wires to connect the cells.
If you use less than 80% of the cells, then probably:
there are optimizations that will increase performance and still allow the design to fit on the chip;
or
you spent too much human effort on optimizing for low area;
or
as possible try to ensure that all ip and op use same clock,then clock clock does not impose any constraints on where the place-and-route tool puts ip- ops and gates. If different ip- ops used different clocks,then ip- ops that are near each other would probably be required to use the same clock.
Use only one edge of the clock signal
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