Rules | Recent posts | topic RSS | Search | Register  | Log in

TMAX's questions

 
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital)
Author Message
binbin1994



Joined: 16 Jun 2008
Posts: 4
Post19 Jun 2008 7:15   TMAX's questions
in TMAX, after ATPG, how can I verify that the pattern is work or not?

use the " Simulation" or "run fault_sim" or both of them?

they are only verify the pattern's logic?

do i need to creat the verilog-environment to run the post-sim to verify the pattern ?

thanks!
Back to top
vlsi_eda_guy



Joined: 08 Feb 2008
Posts: 70
Helped: 7
Post19 Jun 2008 16:48   Re: TMAX's questions
Hi binbin,

You can verify the pattern in Tetramax with just run_sim. But I will not be contended with the results of Tetramax. The reasons are

* Tetramax created the pattern and now you are asking it to verify. So, if it has done some wrong assumption during generating the pattern then it will use the same assumption while validating it .

* Tetramax does not takes timing in account

So to really verify the patterns simulate it in a simulator. (VCS etc...)

-cheers
vlsi_eda_guy
Back to top
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital)
Page 1 of 1 All times are GMT + 2 Hours


Abuse
Administrator
Moderators
topic RSS 
sitemap