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alam.tauqueer
Joined: 19 Jun 2007
Posts: 128
Helped: 3
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 19 Jun 2008 6:52 reset synchronizer |
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Hi,
Can anyone explain me why reset synchronizer used?
And why asynchronous reset deassertion should be synchronized?
Regards,
Tauqueer
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pini_1
Joined: 18 Jun 2007
Posts: 103
Helped: 7
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| 19 Jun 2008 7:01 Re: reset synchronizer |
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Think about a case where you have two FF devices: say FFA and FFB and FFA output drives FFB input. If reset is not synchronized to FF clock, it is possible that on reset de-assert FFB will not see the correct value from FFA. If, however, you do synchronize FFB always see FFA's initial value.
If you use an FPGA make sure you use a FF device without reset. When I had to do it very long ago, I used a synchronous RAM and tied all its inputs to make it behave like an FF.
Lots of VHDL/VERILOG and useful linux scripts at
http://bknpk.no-ip.biz/
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sree205
Joined: 13 Mar 2006
Posts: 417
Helped: 30
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| 19 Jun 2008 12:50 reset synchronizer |
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For any asynchronous signal used in a synchronous domain, there are two time constraints called recovery and removal contrainsts. These should be satisfied to ensure glitch free operation.
The resets should be synchronously deasserted to overcome removal time constraints associated with the reset.
Added after 1 minutes:
Here is a link with detailed discussion and explanation of async/sync resets
http://www.deepchip.com/items/0409-11.html
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alam.tauqueer
Joined: 19 Jun 2007
Posts: 128
Helped: 3
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| 26 Jun 2008 13:42 reset synchronizer |
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References are very good ...and now I got the idea why reset synchronizer used for asynchronous reset.
Thanks alot
Regards,
Tauqueer
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wkong_zhu
Joined: 13 Nov 2004
Posts: 162
Helped: 2
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| 27 Jun 2008 2:23 reset synchronizer |
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reset synchronization is used to make sure the initial condition is what you want.
If the state registers are not reset at the same clock cycle, it may crash the whole system.
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