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vidyaredy
Joined: 31 Jan 2008
Posts: 51
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 17 Jun 2008 13:19 Need code for generating clock doubler using DCM... |
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Hi friends,
This is vidya, I am designing a clock doubler(frequency multiplier) using DCM LOGIC in VHDL. I am finding difficulty in using lang constructs. In which i need to multiply the input clock by 2 when (input clock'event and feedback clock'event)='1'. Plz do the needful if u have idea about how ti implement the logic.....Loads of Thanks in advance...
regards,
vidya
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echo47
Joined: 07 Apr 2002
Posts: 4205
Helped: 564
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| 18 Jun 2008 4:09 Need code for generating clock doubler using DCM... |
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| If you are trying to infer a DCM by writing behavioral HDL, well, the Xilinx tools don't support that. You need to instantiate the DCM primitive into your HDL. DCM instantiation syntax is described in the Libraries Guide for your particular FPGA. If you need to understand how the DCM operates, see your FPGA user guide and/or data sheet.
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vidyaredy
Joined: 31 Jan 2008
Posts: 51
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| 18 Jun 2008 7:46 Re: Need code for generating clock doubler using DCM... |
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Hi,
Thank u very much for quick response. I have gone thro'the manual acc to it, it wil generate lock out signal='1' and dll output clk2x=2*f(clk_in)....when (clk_'event and clk_fb'event)='1'. Its not supporting this format. And Xilinx ISE will generate dcm instance using architecture wizard but no logic behind and at the end i can only use the instance of that. However I need to write the code for lower level dll.....I can generate frequency multiplication or clock doubler using gates but i need to do with DCM....Plz let me know if u have any idea.
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echo47
Joined: 07 Apr 2002
Posts: 4205
Helped: 564
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| 18 Jun 2008 14:52 Need code for generating clock doubler using DCM... |
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I can't quite understand your second message, sorry.
I don't know VHDL very well, but maybe this Verilog example will help you. It inputs a 50 MHz clock, doubles it to 100 MHz, and then clocks a simple counter. It synthesizes into a Spartan-3, a Virtex-5, and maybe other FPGA types too.
| Code: |
module top (clk50, count);
input clk50; // synthesis attribute period clk "50 MHz";
wire clk50dcm, clk100dcm, clk100;
output reg [7:0] count = 0;
DCM dcm100 (.CLKIN(clk50), .RST(1'b0), .CLKFB(clk50dcm), .CLK0(clk50dcm), .CLK2X(clk100dcm));
defparam dcm100.CLKIN_PERIOD = 20.0;
BUFG buf100 (.I(clk100dcm), .O(clk100));
always @ (posedge clk100) begin
count <= count + 1;
end
endmodule |
That's only an example. The DCM is highly configurable, so be sure to read the user guide and data sheet for your FPGA, and use whichever DCM connections and parameters are appropriate for your project. Some folks prefer to use the wizard instead because it hides many of those details.
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vidyaredy
Joined: 31 Jan 2008
Posts: 51
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| 18 Jun 2008 15:21 Re: Need code for generating clock doubler using DCM... |
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Hi,
The one which u have sent is it the instance for dcm? could u plz explain the main logic, I tried to simulate ur code in ise 8.1 but i failed to get multiplied frequency output.
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echo47
Joined: 07 Apr 2002
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| 18 Jun 2008 15:41 Re: Need code for generating clock doubler using DCM... |
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Yes, my example shows Xilinx DCM instantiation. The DCM simply inputs 50 MHz and outputs 100 MHz. The BUFG is a global clock buffer, necessary for driving the clock net.
I'm using ISE 10.1.01. Here's the display in ModelSim 6.3g. What does your simulation look like? Or did you get error messages?
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vidyaredy
Joined: 31 Jan 2008
Posts: 51
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| 19 Jun 2008 7:20 Re: Need code for generating clock doubler using DCM... |
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Hi,
I am using ISE 8.1I and modelsim 6.1b. I have verified with ISE simulator where I am getting output in z (high impedence state)state and rest all in zero. Do I need to add some more logic into the code u have sent r directly run in s/w? Thank u very much for giving me clues.
Added after 11 minutes:
Hi,
do I need to add lower level modules as BUFFER, COUNTER...and one more query in ur code u have mentioned DCM instance then do I need to code for dcm. I am in hurry and just run ur code in s/w to verify the output. Bit Confused.
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MagixD
Joined: 19 Jun 2008
Posts: 1
Helped: 1
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| 19 Jun 2008 10:27 Re: Need code for generating clock doubler using DCM... |
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Hello,
This is the VHDL code to instance a DCM
| Code: |
DCM_SP_inst : DCM
generic map (
CLKFX_DIVIDE => 5,
CLKFX_MULTIPLY => 8,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => X"8080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (
CLK0 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLKDV => open,
CLKFX => open,
CLKFX180 => open,
LOCKED => open,
PSDONE => open,
STATUS => open,
CLKFB => open,
CLKIN => open,
PSCLK => open,
PSEN => open,
PSINCDEC => open,
RST => open
);
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For an description of the signals, use any Xilinx FPGA datasheet (for example Spartan-3 full datasheet, page 29).
If you connect CLKIN with your input clock, the DCM will output the double frequency on CLK2X.
magixD
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vidyaredy
Joined: 31 Jan 2008
Posts: 51
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| 19 Jun 2008 13:55 Re: Need code for generating clock doubler using DCM... |
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Hi...
This is the code for instantiating in top module rite...
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echo47
Joined: 07 Apr 2002
Posts: 4205
Helped: 564
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| 20 Jun 2008 0:01 Need code for generating clock doubler using DCM... |
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My example is ready to synthesize into an FPGA, although it doesn't constrain pin numbers. To simulate it, you must of course provide a testbench that generates the 50 MHz input clock.
"output in z" - do you mean the counter output is floating? That doesn't make sense, it's a register initialized to zero. Maybe you have disconnected signals somewhere.
If your simulation shows all the other signals are zero, I guess you mean the input clock is also zero. If that's true, then you need to debug your testbench clock generator.
Can you show us your code and simulation output? It's difficult to guess what's wrong without seeing any evidence.
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vidyaredy
Joined: 31 Jan 2008
Posts: 51
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| 20 Jun 2008 9:42 Re: Need code for generating clock doubler using DCM... |
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Hi,
I have provided clock as my input, so I have not written any code to generate to clock. Could you please explain me what are the basic blocks do I require to use DCM from ISE. I am designing Data acquisition system and in that I am giving my ZCD signal as input to DCM and to generate output of 2 times as input clock. And then that is given as input to other DCM,in a similar it continues till 6 dcm modules where i wil generate ADC CLOCK. And with extra logic at third dcm's output I am generating sample and hold control signal and start conversion signal for ADC. I am sending the design block which I am trying ti implement plz go thro' the word doc . I am using some nor, nand logic to generate SHG (sample and hold control) signal adn SOC(start of conversion) which i didnt not show in the file instead mentioned as some logic.I am a fresher in the field so getting confused with it.Plz do the needful.
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echo47
Joined: 07 Apr 2002
Posts: 4205
Helped: 564
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| 20 Jun 2008 14:27 Need code for generating clock doubler using DCM... |
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Which FPGA are you using? How many MHz are you generating? Be sure you don't violate the DCM's maximum output frequency or minimum input frequency.
Xilinx says don't cascade more then two DCMs due to jitter accumulation. Besides, six doublers would give you 64 times frequency, not 12 times frequency. Also, to multiply a clock by 6 or 12, you can use one DCM (the CLKFX output).
DCM jitter (hundreds of picoseconds) will add noise to your ADC signal acquisition. If that's a concern for your project, then you should use a high-frequency input clock and eliminate the DCMs.
I don't understand "what are the basic blocks do I require to use DCM from ISE". What do you mean by "block"? ISE doesn't require any preparation before using a DCM.
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vidyaredy
Joined: 31 Jan 2008
Posts: 51
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| 20 Jun 2008 17:00 Re: Need code for generating clock doubler using DCM... |
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| I am using spartan 3, and min frequency for it is 18MHZ. U have sent the simulated output for dcm rite with 50MHZ input freq and output freq of 100MHZ. Then later u said i need to generate a clock of 50 MHZ using testbench. In the dcm instance they have mentioned BUFG,IBUFG,DCM instances. If u dont mind could u plz send me the all files that u have used to generate 100 MHZ from 50 MHZ...and steps in the order which I have to fallow.....I would like see outputs and verify how actually it works and then I wil decide how I should go further. sorry that I did a mistake in plotting no. of multipliers. What i meant is first pll or dll consists of N=6 and later one with N=12(For first i used 3 dcms with each dcm n=2 clock doubler).
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echo47
Joined: 07 Apr 2002
Posts: 4205
Helped: 564
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| 21 Jun 2008 1:29 Need code for generating clock doubler using DCM... |
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I have no more files.
My testbench won't help you -- it won't work with ISE Simulator.
I don't know how to use ISE Simulator, sorry. It probably provide some easy way to generate a clock.
Your words are unclear -- what input and output frequencies do you need?
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vidyaredy
Joined: 31 Jan 2008
Posts: 51
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| 24 Jun 2008 12:19 Re: Need code for generating clock doubler using DCM... |
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Hi,
I have written a code to generate freq doubler its working fine with vhdl but not in verilog. My software is generating only verilog DCM instances. I have attached my files of DCM, DCM instance, clock doubler and top module. Could u plz check the clock doubler code let me know where I have gone wrong....?
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echo47
Joined: 07 Apr 2002
Posts: 4205
Helped: 564
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| 25 Jun 2008 1:19 Need code for generating clock doubler using DCM... |
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I think you are having difficulty writing a Verilog testbench. Your clk50 module contains syntax errors (it won't compile), integer division that gives zero result, and it never instantiates the module to be tested.
Try this. I added a simple testbench module that generates a 50 MHz clock:
| Code: |
// synthesis translate_off
`timescale 1 ns / 1 ps
module testbench;
reg clock = 1;
always #10 clock <= ~clock; // 50 MHz clock
top top (.clk50(clock)); // instantiate the top module
endmodule
// synthesis translate_on
module top (clk50, count);
input clk50; // synthesis attribute period clk "50 MHz";
wire clk50dcm, clk100dcm, clk100;
output reg [7:0] count = 0;
DCM dcm100 (.CLKIN(clk50), .RST(1'b0), .CLKFB(clk50dcm), .CLK0(clk50dcm), .CLK2X(clk100dcm));
defparam dcm100.CLKIN_PERIOD = 20.0;
BUFG buf100 (.I(clk100dcm), .O(clk100));
always @ (posedge clk100) begin
count <= count + 1;
end
endmodule |
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vidyaredy
Joined: 31 Jan 2008
Posts: 51
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| 25 Jun 2008 8:40 Re: Need code for generating clock doubler using DCM... |
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Hi,
I tried with ur testbench for clock its working fine. Now the issue is when I simulated the DCM module I got the error as,
E:/TRY/DCM.v(50): Instantiation of 'DCM' failed. The design unit was not found.
# Region: /dcm2x,.
Do I need to write a code for DCM_INST, again the question raised to me was logic for that, I just did the input assignments to output and named it as DCM_INST.
At the end when I simulated the DCM module I got the erros as..
E:/TRY/DCM.v(51): Unresolved reference to 'CLK_FEEDBACK' in DCM_INST.CLK_FEEDBACK.
# Region: /dcm2x
# ** Error: (vsim-3043) E:/TRY/DCM.v(54): Unresolved reference to 'CLKFX_MULTIPLY' in DCM_INST.CLKFX_MULTIPLY.
# Region: /dcm2x
# ** Error: (vsim-3043) E:/TRY/DCM.v(56): Unresolved reference to 'CLKIN_PERIOD' in DCM_INST.CLKIN_PERIOD.
# Region: /dcm2x
# ** Error: (vsim-3043) E:/TRY/DCM.v(5 : Unresolved reference to 'DESKEW_ADJUST' in DCM_INST.DESKEW_ADJUST.
# Region: /dcm2x
# ** Error: (vsim-3043) E:/TRY/DCM.v(59): Unresolved reference to 'DFS_FREQUENCY_MODE' in DCM_INST.DFS_FREQUENCY_MODE.
# Region: /dcm2x
# ** Error: (vsim-3043) E:/TRY/DCM.v(60): Unresolved reference to 'DLL_FREQUENCY_MODE' in DCM_INST.DLL_FREQUENCY_MODE.
# Region: /dcm2x
# ** Error: (vsim-3043) E:/TRY/DCM.v(61): Unresolved reference to 'DUTY_CYCLE_CORRECTION' in DCM_INST.DUTY_CYCLE_CORRECTION.
# Region: /dcm2x
# ** Error: (vsim-3043) E:/TRY/DCM.v(62): Unresolved reference to 'FACTORY_JF' in DCM_INST.FACTORY_JF.
# Region: /dcm2x
# Error loading design
Sorry the images are too big I 'm not able to attach with this mail, that why I have copied the text msg...
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echo47
Joined: 07 Apr 2002
Posts: 4205
Helped: 564
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| 26 Jun 2008 9:57 Need code for generating clock doubler using DCM... |
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I'm not clear which code you are trying to simulate. If my 24-Jun-2008 example is working fine, then which code is causing all those error messages?
To avoid confusion, upload your HDL files in a ZIP or RAR archive. Don't use a Word document.
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vidyaredy
Joined: 31 Jan 2008
Posts: 51
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| 26 Jun 2008 15:11 Re: Need code for generating clock doubler using DCM... |
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Please find the attached zip file. which consists of codes for clock generator with 50MHZ freq, DCM,buf, ibuf, top module. When I simulate DCM and top module I am getting error as DCM instance not found.
Please let me know where I am going wrong....
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echo47
Joined: 07 Apr 2002
Posts: 4205
Helped: 564
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| 27 Jun 2008 2:42 Need code for generating clock doubler using DCM... |
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| You shouldn't need to create any modules for Xilinx primitives like BUFG or IBUFG. Maybe you haven't finished installing your simulator. See section "Compiling the Xilinx Simulation Libraries" in your ISE "Synthesis and Simulation Design Guide". That step is essential for simulation, unless you are using the special Xilinx version of ModelSim that includes pre-compiled simulation libraries. That would also explain "DCM not found".
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vidyaredy
Joined: 31 Jan 2008
Posts: 51
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| 27 Jun 2008 11:01 Re: Need code for generating clock doubler using DCM... |
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Hi,
I have simulated these files in modelsim 6.1b. when I simulated in ISE simulator 8.1i , OUTPUT was in z state....Sorry I am not finding the section Compiling the Xilinx Simulation Libraries in Xilinx Synthesis and Simulation Design Guide. I am using Xilinx ISE 8.1i. Is it possible for u to make some alterration in my code and revert me back. will be great help....
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echo47
Joined: 07 Apr 2002
Posts: 4205
Helped: 564
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| 27 Jun 2008 11:19 Need code for generating clock doubler using DCM... |
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The section "Compiling Xilinx Simulation Libraries" is on page 234 of the ISE 8.1i Synthesis and Simulation Design Guide.
http://www.xilinx.com/support/sw_manuals/xilinx8/download/sim.zip
Which version of ModelSim do you have? Is it PE, SE, XE, ... ?
I think XE includes pre-compiled libraries, but the other vesions do not, so you must compile them.
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vidyaredy
Joined: 31 Jan 2008
Posts: 51
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| 27 Jun 2008 13:52 Re: Need code for generating clock doubler using DCM... |
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Hi,
I am using modelsim SE 6.1b. Compling means normal way of compling or something diff.... I did compling before simulating....it was successful.
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echo47
Joined: 07 Apr 2002
Posts: 4205
Helped: 564
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| 27 Jun 2008 14:14 Need code for generating clock doubler using DCM... |
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No, compiling the simulation libraries as described in the Xilinx manual is a special operation that takes many minutes and generates a huge directory of files.
Also, whenever you update your ISE or ModelSim installation, you probably should recompile these libraries.
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vidyaredy
Joined: 31 Jan 2008
Posts: 51
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| 28 Jun 2008 14:22 Re: Need code for generating clock doubler using DCM... |
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Hi,
I have complied all the simluation libraries-unisim,simprim, xilinx corelib... I am not getting DCM output itself I mean to say double the clock freq(clk2x). I am able to get clko. Do I need to make any changes in the DCM generated by ISE, could u plz look into the waveform and let me know where I have gone wrong.
Added after 35 minutes:
Hi,
I have one doubt, the DCM code generated by ISE consists of one more DCM INST in it. Do I need to port map those to Top module or main DCM ports? When I have portmapped top module with DCM main ports, I am getting error as mutilple drivers. When I portmap with DCM INST and defparam dcm100.CLKIN PERIOD = 20.0; being declared in the topmodule I am getting error as
expecting '=', found 'PERIOD'...
Could u plz tell me any error in the code generated by DCM. And which ports do I need to instatiate in my top module.
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echo47
Joined: 07 Apr 2002
Posts: 4205
Helped: 564
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| 28 Jun 2008 18:09 Need code for generating clock doubler using DCM... |
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Ok, good job compiling the libraries.
Your JPEG image is helpful, but it doesn't show the time axis. Be sure your clock is really 50 MHz (20ns).
Please upload your current source code and testbench. I can't quite follow your description about ports, and I can't guess what code your version of ISE has generated, or which options you've selected.
My defparam statement works with a DCM primitive. It probably won't work with some module generated by ISE.
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vidyaredy
Joined: 31 Jan 2008
Posts: 51
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| 29 Jun 2008 9:31 Re: Need code for generating clock doubler using DCM... |
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when I compile my top module I am getting the error as....
ERROR:Xst:528 - Multi-source in Unit <clock2x> on signal <clk50dcm>,
we have clk50 for both drivers. And output is not generated for clock2x from DCM. Plz find the attached files of my code.
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echo47
Joined: 07 Apr 2002
Posts: 4205
Helped: 564
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| 29 Jun 2008 12:54 Re: Need code for generating clock doubler using DCM... |
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I see some problems in your clock2x module:
- Signal clk50dcm shorts together two output ports.
- Too many BUFGs. The dcm2x module already buffers the 100 MHz clock.
- Verilog is case-sensitive. Change 'LOCKED' to 'locked'.
Try this. It simulates fine with your dcm2x and testbench modules:
| Code: |
module clock2x (clk50, count, locked);
input clk50; // synthesis attribute period clk "50 MHz";
wire clk100;
output reg [7:0] count = 0;
output locked;
dcm2x dcm100 (.CLKIN_IN(clk50), .RST_IN(1'b0), .CLKIN_IBUFG_OUT(), .CLK0_OUT(), .CLK2X_OUT(clk100),.LOCKED_OUT(locked));
always @ (posedge clk100)
begin
count <= count + 1;
end
endmodule |
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vidyaredy
Joined: 31 Jan 2008
Posts: 51
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| 29 Jun 2008 19:44 Re: Need code for generating clock doubler using DCM... |
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Its not working, when I simulate the DCM I am not getting outputs for clk2x,locked signals. when I wont get output in DCM, the same I am instatiating in Clock2x top module. Thus I am getting error output in both of these. One more query I am using testbench na do I need to force clock in DCM? These are my latest waveforms of DCM and clock2x, after changes made acc to u....
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echo47
Joined: 07 Apr 2002
Posts: 4205
Helped: 564
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| 30 Jun 2008 6:20 Need code for generating clock doubler using DCM... |
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I don't know why it doesn't work for you. Maybe your version of ISE has a bug. Be sure you've installed the latest service packs.
Also try applying a reset pulse to the DCM. The pulse duration should be at least three clock cycles.
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