Need Help in Parallel to Serial VHDL module

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missbirdie

Joined: 21 May 2008
Posts: 35
Location: Egypt

10 Jun 2008 22:47 parallel to serial vhdl

Hello
I have a question about the following VHDL code to convert from parallel to serial:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity PAR2SER is
Port ( DIN : in STD_LOGIC;
MODE : in STD_LOGIC;
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
SDOUT : out STD_LOGIC);
end PAR2SER;

-- purpose: Implement main architecture of PAR2SER

architecture BEHAVIOR of PAR2SER is

signal IDATA : std_logic_vector(7 downto 0); -- internal data

begin -- BEHAVIOR

-- purpose: Main process

process (CLK, RESET)
begin -- process
-- activities triggered by asynchronous reset (active high)
if RESET = ’1’ then
SDOUT <= ’0’;
IDATA <= "00000000";

-- activities triggered by rising edge of clock

elsif CLK’event and CLK = ’1’ then
case MODE is
when "00" => -- no operation
null;
when "01" => -- load operation
IDATA <= DIN;
when "10" => -- shift left
SDOUT <= IDATA(7);
for mloop in 6 downto 0 loop
IDATA(mloop+1) <= IDATA(mloop);
end loop; -- mloop
when others => -- no operation otherwise
null;
end case;
end if;
end process;
end BEHAVIOR;

I may sound silly but what's the mode pin for ??

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FvM

Joined: 22 Jan 2008
Posts: 5156
Helped: 767
Location: Bochum, Germany

11 Jun 2008 8:11 parallel to serial shift register vhdl

The author apparently regarded it useful to control serializer operation with a mode input. There are other options, too. You have to know your requirements.

But the code has a syntactical error, cause mode input is a single std_logic bit but used as a vector. It can't compile as is.

mmarco76

Joined: 04 Jan 2008
Posts: 85
Helped: 6

11 Jun 2008 13:30 parallel to serial vhdl code

True what FvM says.
Moreover I've to tell you that this is a very bad way of code VHDL.
The construct FOR shall never being used: that's not "C".

You can do in a lot of different manner, the better I think is instantiate a counter and use a shift register.
In VHDL you've to figure out what are you realizing with the Flip Flop.