difference on the post-layout and pre-post-layout simulation

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kDaniu

Joined: 18 Jun 2007
Posts: 33
Helped: 9
Location: UA->Korea

04 Jun 2008 6:38 pre post simulation

hello all
I have some strange results in post-layout hspice simulation and can not understand the problem. maybe you know more about ...
so, f,e, I have a simple ring oscillator
when I making a hspice simulation, the oscillation frequency is 7.8ns
but when I making the post-layout hspice simulation (of 'the same' ring oscillator) I have a 10.8ns oscillation period.
I understand, that difference between the simple (schematic) hspice simulation and post-layout hspice simulation in the nodes (last one take account the resistance and capacitance of interconnections, but why the period of oscillation changed so much (~30% ) ?
any ideas ?

thanks,
Dan

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kDaniu

Joined: 18 Jun 2007
Posts: 33
Helped: 9
Location: UA->Korea

09 Jun 2008 3:16 difference on the post-layout and pre-post-layout simulation

sorry community, but up
because the question is still actual

turtleden

Joined: 15 Sep 2006
Posts: 38
Helped: 3

10 Jun 2008 7:58 difference on the post-layout and pre-post-layout simulation

I guess it's because of the para cap.

kDaniu

Joined: 18 Jun 2007
Posts: 33
Helped: 9
Location: UA->Korea

10 Jun 2008 8:09 Re: difference on the post-layout and pre-post-layout simula

turtleden wrote:

I guess it's because of the para cap.

I wrote about that in my first post, but imho the 30% of difference it's too much betweeen the schematic and post-layout hspice simulation...
any other reasons?
or in real you guys saw similar effect after post-layout ?

layes2

Joined: 03 Dec 2004
Posts: 346
Helped: 5

11 Jun 2008 9:13 difference on the post-layout and pre-post-layout simulation

add cap yourself or by rc ext

kDaniu

Joined: 18 Jun 2007
Posts: 33
Helped: 9
Location: UA->Korea

11 Jun 2008 9:46 Re: difference on the post-layout and pre-post-layout simula

layes2 wrote:

add cap yourself or by rc ext

added.... values were related to the real caps values between the cascades...
the difference was not so much Sad

sachin_kirdat

Joined: 02 Jun 2008
Posts: 34

11 Jun 2008 10:59 difference on the post-layout and pre-post-layout simulation

Make sure you are simulating on same process/vlotage/temp corener.

Blackuni

Joined: 12 Apr 2007
Posts: 196
Helped: 25

11 Jun 2008 22:58 Re: difference on the post-layout and pre-post-layout simula

Hi,

My method may not be direct but it is worth 2 try

1. Check delay of individual cell in the ring oscillator for the post layout netlist against prelayout.

My 2nd suggestion might be bit deviating but it has a fair chance of finding the cause.

I think u are aware of Back Annotation flow where U will have extracted parasitics (SPF r SPEF) and it will BA to prelayout netlist.

IF u have SPF r SPEF then
1. BA only the interconnect part ( don't BA instance part) check the period oscillation. if the period is close 2 prelayout then problem is with u r MOS layout
2. do BA for only instance part check the period of oscillation

Wish i m explicit. Please let me know for any clarification.

thanks,

kDaniu

Joined: 18 Jun 2007
Posts: 33
Helped: 9
Location: UA->Korea

11 Jun 2008 23:59 difference on the post-layout and pre-post-layout simulation

thanks Blackuni, will test

mdcui

Joined: 23 Aug 2005
Posts: 110
Helped: 22
Location: China shanghai

12 Jun 2008 4:06 Re: difference on the post-layout and pre-post-layout simula

I used to have a output buffer simulation before and post layout extraction, easily the difference could be 0.4ns for a total delay of 6-7ns, so layout parasitic RC could be bigger than you expected.

RF-OM

Joined: 03 Aug 2007
Posts: 607
Helped: 113
Location: The Earth

12 Jun 2008 6:29 Re: difference on the post-layout and pre-post-layout simula

There is always the difference and always post-layout result shows longer delays. The reason lays in different models and in parasitics. When you do your first simulation try to include as much element modeling and parasitic as you can. In next round of simulation you may correct these values. Something between 5 and 25 % of the difference can be considered as normal. As more you are experienced as less will be this difference. I am sure you will see it soon.

Best regards,
RF-OM

kDaniu

Joined: 18 Jun 2007
Posts: 33
Helped: 9
Location: UA->Korea

12 Jun 2008 6:35 Re: difference on the post-layout and pre-post-layout simula

mdcui wrote:

I used to have a output buffer simulation before and post layout extraction, easily the difference could be 0.4ns for a total delay of 6-7ns, so layout parasitic RC could be bigger than you expected.

that is just cleaning an output
but for me the clear work of every cascade is important ..
in real I found the problem (in the middle components between the RO inverter - in my case that is not clear RO)
thanks for all for your help and respond

best,
Dan

gafsos

Joined: 01 Feb 2006
Posts: 161
Helped: 11
Location: North Africa

16 Jun 2008 14:10 Re: difference on the post-layout and pre-post-layout simula

Before simulation of Ur RO try to take a inverter as a simple testcase and try ti run pre/post simulation.

Beginning from 90 nm technology process and deeper (65nm and 45nm), well proximity effect becomes more significant in alteration of MOS device characteristics

•Pre-layout simulation (schematic + NoRC mode)
•Post-layout simulation
•Post-layout simulation with extracting SCA, SCB and SCC parameters

A+

kDaniu

Joined: 18 Jun 2007
Posts: 33
Helped: 9
Location: UA->Korea

17 Jun 2008 1:49 Re: difference on the post-layout and pre-post-layout simula

I have to point

Blackuni wrote:

IF u have SPF r SPEF then
1. BA only the interconnect part ( don't BA instance part) check the period oscillation. if the period is close 2 prelayout then problem is with u r MOS layout
2. do BA for only instance part check the period of oscillation

that info was realy helpful and we found more bugs then expected Very Happy

. I'm newbie in that are so that is why so simple things were new for me.

anyway, it's working now and I thnx for all for your attention and help

b.t.w. some bugs happened not from the schematic/functionality (my responsibility) reason but through the layout; that is why I'm interested right now in some information about layout of parallel inverters with an increased width and length; path gate (mux)
if anybody has any metherial related to that kinds of layout that will be very helpul
thanks for all

regards,
Dan