How to work with FPGA cores?

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Jayson

Joined: 08 Oct 2001
Posts: 457
Helped: 17

24 Dec 2002 20:49 How to work with FPGA cores?

I am very unfamiliar with FPGA cores. So bear with my ignornance a bit.

I've seen many people refer to cores as if they were very common, but how does someone use a CORE made by someone else?

I have seen a 8051 VHDL core floating around but how does someone use it, what is it good for? Does Xilinx Foundation support the use of cores? if so how?

- Jayson

vomit

Joined: 14 Jun 2002
Posts: 144
Helped: 10

24 Dec 2002 22:38

It depends on the type of core. A soft-core is delivered as a piece of HDL that you can synthesize along with your own HDL.
A hard-core is delivered as an (possibly even encrypted) netlist of gates (often EDIF-format) that you can still compile in your fitting tool. But if you look at the EDIF you won't find any meaningful netlist names so reverse engineering it would not be worthwile the effort.

Some tools encrypt the EDIF and have decryption keys built into the fitting tool so the user cannot see anything. The only thing you could look at is the post-place-and-route netlist. So there's not much to see, and making modifications is totally out of the question.

Hope this helps...

Jayson

Joined: 08 Oct 2001
Posts: 457
Helped: 17

25 Dec 2002 15:35

But what can you do with a core?
Why even use cores? are people too lazy to create their own stuff?

- Jayson

Bartart

Joined: 20 Feb 2002
Posts: 127

25 Dec 2002 17:50

Hi!

Why even use cores?

Think about DDC (digital down converter) core, I am workin on it for about 6 months and still nothing. The DDC is composed by multipliers, CIC FIR filters and SM to control all.

You can crate your own code (5 months) then you use simulator (1 month) and finaly you or your boss figure it out that this is not worth of your time.

that is why people use cores - time time time.

Bart

Jayson

Joined: 08 Oct 2001
Posts: 457
Helped: 17

25 Dec 2002 19:46

okay I have a VHDL 8051 core, how do I do something with it? How do I use inputs and outputs? How do I download my ASM compiled HEX code into it? What is the method from 1. obtaining core to 2. actually making use of it?

- Jayson

ccljpeg

Joined: 08 Dec 2001
Posts: 33

26 Dec 2002 3:45

hi:
1.If you have VHDL core (8051) then use Xilinx FPGA to implement
you core. So you have real 8051 device.
implement way :
a. use Xilinx ISE5.1 to synthesis VHDL core , place and route, to get
VHDL netlist
b. post simulation VHDL netlist , if timing ok, then you get real 8051

2. design 8051 , EEPROM circuits, and you can put binary format
assembly in EEPROM , then you have small 8051 ststem

apacz

Joined: 20 Apr 2002
Posts: 29

26 Dec 2002 16:47

You may try use WebPack (you'll find it at www.xilinx.com). It is freeware.

ljkong

Joined: 18 Jul 2002
Posts: 128
Helped: 1
Location: P.R.C

04 Jan 2003 3:09

in fact, if you have no specaial idea of yourself, it is no use you do this. you have no any advantage.

everyone know ASIC8051 is very cheap,.

dinolin

Joined: 19 Jul 2002
Posts: 39
Helped: 1

04 Jan 2003 5:03

apacz wrote:

You may try use WebPack (you'll find it at www.xilinx.com). It is freeware.

you are right,
but WebPack can't support some advanced FPGA, for eg, X2CV6000 ...

ljkong

Joined: 18 Jul 2002
Posts: 128
Helped: 1
Location: P.R.C

15 Jan 2003 10:45

i think if you hope to use ip core,
the third-part tools are better.

Ohh

Joined: 31 May 2001
Posts: 51

15 Jan 2003 11:33

Why IP cores?
I think, good IP cores can significantly reduce your time to market. This is true for both SOC
and FPGA design.

madmax

Joined: 10 Jan 2003
Posts: 12

15 Jan 2003 16:52

Hi ,

If it is a soft core,compile the core.

You instantiate the core in your code.

Then compile and synthesis it. Make the total design work according to your requirement by place and route.

lockerman

Joined: 08 Oct 2001
Posts: 47

22 Jan 2003 23:15

It's very simple.

Take the core, instantiate it as many times as you want and download it into FPGA. This way u can create pretty complex systems on FPGA.

Would be nice to have A/D on FPGAs, would not be Smile

.

Lm

ramesh

Joined: 19 Jan 2003
Posts: 1234
Helped: 4

23 Jan 2003 5:28

Hi Lockerman

I agree with you. In addition to having ADC alone, having ADC & DAC would be very nice for DSP applications.

Bartart

Joined: 20 Feb 2002
Posts: 127

23 Jan 2003 8:11

Hello!

ADC or DAC on FPGA like "russian spacecraft jurney to Mars" you will never see that.

But there is a ADC core you can use.

go to www.nov@-eng.com

Bart

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