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Slew Rate


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quaternion



Joined: 12 Nov 2006
Posts: 209
Helped: 11
Location: Cairo , Egypt


Post14 May 2008 3:35   

Slew Rate


How is the slew rate of a pmos OTA is larger than that of a nmos OTA?

For normal differential input single ended output OTA , Is the slew rate depends on the polarity of the input signal and on the type of the OTA (nmos or pmos) [i.e. the polarity of signal resulting in smaller slew rate is reversed for different type ]?


I know that these issues are in text books but they still unclear for me.
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kwkam



Joined: 25 Feb 2002
Posts: 299
Helped: 15
Location: Somewhere on earth


Post14 May 2008 16:04   

Slew Rate


No, usually slew rate depends on the input differential pair tail current and internal compensation capacitor. Of course, in some case SR can also depends on other parameter because of the opamp architectural.
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quaternion



Joined: 12 Nov 2006
Posts: 209
Helped: 11
Location: Cairo , Egypt


Post14 May 2008 20:22   

Re: Slew Rate


kwkam wrote:
Of course, in some case SR can also depends on other parameter because of the opamp architectural.


So for single ended output amplifier which signal polarity suffers a smaller slew rate ? & why?
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supreet_95



Joined: 23 Sep 2007
Posts: 51
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Location: bangalore


Post15 May 2008 5:48   

Slew Rate


The slew rate in decided by the bias current of the last stage. If ur using the a single stage it will depend on the common bias current and if two stage then the 2nd stage (inverter with active load) current. It wont be cause any difference if u apply signal to any one of the inputs. Since it is a diffrential structure u will get the same output current strength. Inputs will only decide the polarity.
Hope this helps.
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Post15 May 2008 5:48   

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quaternion



Joined: 12 Nov 2006
Posts: 209
Helped: 11
Location: Cairo , Egypt


Post15 May 2008 15:34   

Re: Slew Rate


I am wandering; If we have simple nmos input OTA (single ended output 1-stage) that is loaded by a cap, for different polarities(equal amplitude) large input signal the circuit configuration will differ (the off transistor once will be at the ouput & once in the other side), So how the cap charging rate will be the same in both cases although the charging path has changed ?
[Current is once supplied from the upper pmos & once driven by the 2 lower nmos's]

Please , if I am wrong ,anyone could tell me !
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