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anishjp
Joined: 04 Jan 2008
Posts: 44
Location: "Gods own country".. Kerala
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 13 May 2008 10:56 Clock Gating |
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Hi all,
What is the effect of clock gating in design.....?
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AdvaRes
Joined: 14 Feb 2008
Posts: 456
Helped: 20
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| 13 May 2008 11:14 Re: Clock Gating |
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| anishjp wrote: |
Hi all,
What is the effect of clock gating in design.....? |
It is a low power techniques. What do you mean by effect ?
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phoenix_pavan
Joined: 10 May 2008
Posts: 24
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| 13 May 2008 17:20 Clock Gating |
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| It can lead to glitches even though it is used a low power t/q and it can be done in several ways like using an and gate.But, a latch implementation is widely used to avoid glitches
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anantha_09
Joined: 28 Jan 2007
Posts: 74
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| 13 May 2008 17:58 Re: Clock Gating |
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>>>>>It can lead to glitches even though it is used a low power t/q and it can be done in several ways like using an and gate.***But, a latch implementation is widely used to avoid glitches *****
latches are prone to glitches coz of enable being high.
F/F avoid glitches
Added after 18 seconds:
>>>>>It can lead to glitches even though it is used a low power t/q and it can be done in several ways like using an and gate.***But, a latch implementation is widely used to avoid glitches *****
latches are prone to glitches coz of enable being high.
F/F avoid glitches
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flatulent
Joined: 19 Jul 2002
Posts: 4814
Helped: 279
Location: Middle Earth
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| 14 May 2008 1:09 Re: Clock Gating |
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| One thing to avoid is using a gating method that will produce a pulse below the minimum required to clock the following circuits. Some will clock and some will not which will put your system into an indeterminate state.
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vlsi_eda_guy
Joined: 08 Feb 2008
Posts: 57
Helped: 6
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| 14 May 2008 21:31 Re: Clock Gating |
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DFT is another thing to consider when doing clock gating..
-cheers
vlsi_eda_guy
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badola
Joined: 04 Jan 2008
Posts: 85
Helped: 1
Location: bangalore
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| 15 May 2008 5:12 Re: Clock Gating |
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| For gated clocks or derived clocks: a test mode should be implemented that will driveall the Flip-Flop (FF) clocks from a single test clock during this test mode. Also, clock skew for this test clock should be properly balanced so there are no hold violations on any of the registers both during scan shift and normal mode.
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anishjp
Joined: 04 Jan 2008
Posts: 44
Location: "Gods own country".. Kerala
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| 15 May 2008 11:51 Re: Clock Gating |
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| AdvaRes wrote: |
| anishjp wrote: |
Hi all,
What is the effect of clock gating in design.....? |
It is a low power techniques. What do you mean by effect ? |
Hi AdvaRes,
Thanks for the reply, Can u explain me how it saves power...?
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AdvaRes
Joined: 14 Feb 2008
Posts: 456
Helped: 20
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| 15 May 2008 12:02 Clock Gating |
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Hi anishjp,
It's quite simple. Suppose that you have a system composed of differents sub-systems which are clocked with the same or differents clocks CLK1, CLK2.....
In some case/application some sub-systems are not used all the time so we swich them of by desabling their corresponding clocks. This saves power since it woould no longer be a consumed dynamic power becase transistors of this subsystem does not switch.
Hope it helped !
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aru_vlsi
Joined: 22 Aug 2007
Posts: 6
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| 16 May 2008 12:30 Re: Clock Gating |
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It is basically used to save the Dynamic Power in the design.
Clock gate can consist of some gate(AND/OR/NOR/NAND) and a latch. This is called discrete clock gating.
It may be present in the library as a single entity.That is called Integrated Clock Gating.
Discrete is prone to glitches whereas the later one is free from glitches.
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alpeshchokshi
Joined: 05 Mar 2006
Posts: 146
Helped: 4
Location: San Jose, CA
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| 27 May 2008 0:03 Re: Clock Gating |
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| clk gating is used for power saving... at the same time in DFT its required for testmode and normal mode.
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newcpu
Joined: 30 Oct 2005
Posts: 80
Helped: 2
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| 27 May 2008 3:11 Clock Gating |
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| Glitches can be avoid by using ICG cell in the library.
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