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parasitics redution

 
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chinni_25



Joined: 06 May 2008
Posts: 5


Post13 May 2008 10:53   parasitics redution

The main problems of layout for analog/mixed signal ICs are device matching and unwanted parasitics reduction.

In this what's the meaning of parasitics redution?
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vlsitechnology



Joined: 01 Nov 2007
Posts: 214
Helped: 6


Post15 May 2008 11:17   parasitics redution

Parasitics reduction is nothing but reducing the R and C values that is delay...
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moriar



Joined: 28 Aug 2007
Posts: 21
Helped: 3


Post16 May 2008 9:04   parasitics redution

What VLSItech said is correct. To elaborate, when you draw a metal line say in one layer, you should realize that this metal line, especially in high frequency is not just a line, so to speak. If you have done RF before, the idea is similar. A strip of metal is both a resistor and or even an inductor and its relation to other strips of metal through insulator is obviously a capacitor.

This effect becomes important for "critical" path lines because of signal integrity issues. So when you do routing, you have to bear in mind what parasitics can do to the design.
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