Rules | Recent posts | topic RSS | Search | Register  | Log in

Duty cycle control of the clock

 
Post new topic  Reply to topic    EDAboard.com Forum Index -> Analog IC Design & Layout
Author Message
taofeng



Joined: 21 Mar 2006
Posts: 92
Helped: 1


Post12 May 2008 21:27   Duty cycle control of the clock

Hi,

I need some help to generate a clock signal with 50/50, 40/60, 30/70 , 20/80 and 10/90 duty cycle combination. thanks a lot !

jeffrey
Back to top
zhongdg



Joined: 03 Apr 2008
Posts: 65
Helped: 1


Post13 May 2008 8:14   Re: Duty cycle control of the clock

You can adjust the PMOS and NMOS size to control the duty cycle of the clock.
Another way is to add RC delay cell at different node of inverter path to control the duty cycle.
Back to top
menz



Joined: 14 Feb 2008
Posts: 51
Helped: 4


Post13 May 2008 9:02   Duty cycle control of the clock

RC time constant will change ur clock tym
Back to top
Post new topic  Reply to topic    EDAboard.com Forum Index -> Analog IC Design & Layout
Page 1 of 1 All times are GMT + 2 Hours


Abuse
Administrator
Moderators
topic RSS 
sitemap