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kalyansumankv
Joined: 30 Dec 2005
Posts: 17
Helped: 1
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 12 May 2008 14:50 synchronous clock domain crossing |
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Hi all,
Can some help me in understanding what is "synchronous clock domain crossing",
what kind of problems we can face from the above, and what are the methods to avoid the same....
Thanks&Regards
Kalyansuman
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anantha_09
Joined: 28 Jan 2007
Posts: 74
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| 13 May 2008 18:03 Re: synchronous clock domain crossing |
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http://www.edadesignline.com/howto/205201913?pgno=3
http://www.asic-world.com/tidbits/clock_domain.html
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kalyansumankv
Joined: 30 Dec 2005
Posts: 17
Helped: 1
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| 14 May 2008 6:11 Re: synchronous clock domain crossing |
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Dear Anantha,
thanks a lot for your reply,
the link one is that which speaks about a Asynchronous clock domain crossing,
and second link is also of same kind of stuff,
But what am speaking is synchronous clock domain crossing,
i.e., there will be a relation between both the clock domain, as they will be generated from the same clock source.
for example there will a clock domain clka with 80Mhz and the other clk_b with 20Mhz,i want to know what kind of measures to be taken when the data is transferred between these clock domains.
I will be thankful if some one can help in this regard
Regards
KalyanSumankV
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AdvaRes
Joined: 14 Feb 2008
Posts: 601
Helped: 33
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| 14 May 2008 10:04 Re: synchronous clock domain crossing |
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| kalyansumankv wrote: |
Dear Anantha,
thanks a lot for your reply,
the link one is that which speaks about a Asynchronous clock domain crossing,
and second link is also of same kind of stuff,
But what am speaking is synchronous clock domain crossing,
i.e., there will be a relation between both the clock domain, as they will be generated from the same clock source.
for example there will a clock domain clka with 80Mhz and the other clk_b with 20Mhz,i want to know what kind of measures to be taken when the data is transferred between these clock domains.
I will be thankful if some one can help in this regard
Regards
KalyanSumankV |
Hi,
I dont know if you are asking for clock synchronization or data synchronization.
For clock synchonisation even if Clk1 is a natural multiple of Clk2, if Phase Clk1-Phase CLK2 is not null then synchronization will be ensured simply by inserting 2 DFFs between the two clock domain: one DFF is drived by Clk1 that second by CLK2.
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kalyansumankv
Joined: 30 Dec 2005
Posts: 17
Helped: 1
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| 14 May 2008 10:39 Re: synchronous clock domain crossing |
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Hi,
I am actually speaking about data synchronization,
Thanks for your advice,let me try that and see if
i have any timing violations
Regards
KalyanSumankv
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