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priyankguddu
Joined: 04 Feb 2005
Posts: 85
Helped: 6
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 11 May 2008 19:50 VHDL Simulator related Query |
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hi!
I am in search of a VHDL simulator which satisfy these requirements.
1. I wanted to automate the simulation process, i.e. say i have 1000 separate piece of VHDL code, and i waned to simulate all of them, and store the simulation/ test results in a data file to be analysied by another computer program. So, some sort of scripting would be handy
2. The simulation results should be easily accessible for analysis, as we have to assign a fitness function to the test/simulation results.
3. As, my problem domain is image change detection, it should be able to handle image data as input.
Presently, i am not sure as to which of them to choose, as i hadn't worked on VHDL simulation much. I only have a basic knowledge of Xilinx ISE 8.2i.
Also, tell me how to automate these steps.
well, i am trying Genetic programming on VHDL codes.
Thanking you in advance, i am waiting for reply.
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vomit
Joined: 14 Jun 2002
Posts: 137
Helped: 9
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| 11 May 2008 21:42 Re: VHDL Simulator related Query |
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Try GHDL, it compiles an executable from your VHDL code. It is based on the GNU C/ADA/Java Compiler, but with a VHDL frontend.
1. I wanted to automate the simulation process, i.e. say i have 1000 separate piece of VHDL code, and i waned to simulate all of them, and store the simulation/ test results in a data file to be analysied by another computer program. So, some sort of scripting would be handy
You can make a script calling the executable several times with other parameters
2. The simulation results should be easily accessible for analysis, as we have to assign a fitness function to the test/simulation results.
Use VHDL TextIO to log results to a file
3. As, my problem domain is image change detection, it should be able to handle image data as input.
This is a general problem for VHDL, not simulator dependant. You'll have to write a converter library from a common easy file format, using VHDL procedures. You might be able to link external code to the VHDL executable, but I haven't tried that.
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pini_1
Joined: 18 Jun 2007
Posts: 76
Helped: 3
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| 16 May 2008 15:47 Re: VHDL Simulator related Query |
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I use GHDL. How to compile script can be founs at:
http://bknpk.no-ip.biz/LEON/AHB_APB_leon/AHB_APB_leon.html
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sajjadi335
Joined: 28 Feb 2006
Posts: 16
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| 17 May 2008 8:18 Re: VHDL Simulator related Query |
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| Of course you could do it with ModelSim too. You would have to know TCL and read ModelSim documents carefully to understand the automation process. It also doesn't need Writing TextIO VHDL testbenches and could easily export well-formatted outputs. But for image, sorry, no special library etc is available. You need to do it on your own. I would have used Matlab to generate simple readable files from the images.
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pini_1
Joined: 18 Jun 2007
Posts: 76
Helped: 3
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| 18 May 2008 12:03 Re: VHDL Simulator related Query |
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A regression autmation PERL script example can be seen at
http://bknpk.no-ip.biz/MiscellaneousHW/regFIFO.html
The design is in verilog, but same applies to VHDL.
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ljxpjpjljx
Joined: 05 May 2008
Posts: 84
Helped: 2
Location: Shang Hai
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| 12 Jun 2008 3:44 Re: VHDL Simulator related Query |
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| can some one share with us more template?
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smdunga
Joined: 13 Jun 2008
Posts: 1
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| 13 Jun 2008 18:30 VHDL Simulator related Query |
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right now If u r concentrating only on simulation......then modelsim alone can fulfill ur requirement......
as modelsim supports tcl scripts u can automate ur process by writing some small scripts......
for tis u need to use modelsim in batch mode...
n try to use the FileIO feature in vhdl to store the results in text format......
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