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phoenix_pavan
Joined: 10 May 2008
Posts: 24
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 10 May 2008 18:06 Digital question |
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Someone plz help
1 . There are 2 clocks of the same frequency but with a phase difference. Design a circuit to find which clock is lagging/leading:?:
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sree205
Joined: 13 Mar 2006
Posts: 411
Helped: 30
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| 12 May 2008 7:45 Digital question |
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| If the two clocks are XOR'ed, look for the XOR'ed output 1's posedge to coincide with a clock's posedge and negedge. The other clock is lagging this one.
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surisingh
Joined: 14 Jun 2007
Posts: 19
Helped: 1
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| 12 May 2008 8:22 Re: Digital question |
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Hi,
Design a FF, Give one clock to the CLK input of FF, another clock to D input of FF
Look for the output of FF. If you get the '1' at the first clock, the clock at the D input is leading, else it is lagging.
Please let me know, if it is wrong.
Regards,
CSuresh
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sree205
Joined: 13 Mar 2006
Posts: 411
Helped: 30
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| 12 May 2008 9:04 Digital question |
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| Q will be tied to either 1 or 0 throughout, good solution
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jecyhale
Joined: 19 Feb 2008
Posts: 402
Helped: 39
Location: China
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| 12 May 2008 10:28 Re: Digital question |
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| phoenix_pavan wrote: |
Someone plz help
1 . There are 2 clocks of the same frequency but with a phase difference. Design a circuit to find which clock is lagging/leading:?: |
Use a flip-flop, one is the data and the other is the clock.
Then to check the output of flip-flop, you will get the different result.
If the result is '1', it means the data is the leading one.
Or else the clock is the leading one.
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phoenix_pavan
Joined: 10 May 2008
Posts: 24
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| 12 May 2008 12:32 Re: Digital question |
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Thanx all of you for ur support.
It helped
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nine8
Joined: 18 Sep 2007
Posts: 26
Helped: 1
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| 17 May 2008 16:17 Digital question |
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A DFF can do it easy .
one clock named A is used as Clock
The other is named B used as Input Data
if the output Q is "1", the B is leading,
of the output Q is "0", the A is leading.
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