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rake.405
Joined: 11 Aug 2007
Posts: 16
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 09 May 2008 8:22 drc lvs errors |
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| can anyone give some drc&lvs errors in the asic design
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layoutmaster
Joined: 18 Mar 2008
Posts: 182
Helped: 27
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| 09 May 2008 14:17 drc lvs errors |
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| Please elaborate a little more your question. It's not clear what are you really looking for...
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vlsitechnology
Joined: 01 Nov 2007
Posts: 212
Helped: 6
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| 10 May 2008 11:17 drc lvs errors |
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i think he is asking about the DRC and LVS errors which we usually get after designing the layout...like
open circuit violation, short circuit violation , antenna violation , density check violations and min contact rule and so on am i right?
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kumar_eee
Joined: 22 Sep 2004
Posts: 350
Helped: 4
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| 11 May 2008 10:22 Re: drc lvs errors |
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Hi vlsitechnology, Yes you are right...
Find some more from my experiance.
LVS:
Open circuit
short circuit
Different no.of Ports
Connectivity Error
Property Error
...... etc
DRC:
Latch-Up violation
Min space Error
Metal Enclosure violation
Fat metal Spacing violation
Poly Endcap violation
..etc..
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vlsitechnology
Joined: 01 Nov 2007
Posts: 212
Helped: 6
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| 13 May 2008 6:24 drc lvs errors |
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HI kumar wts this poly end cap violation??
how to minimise this?
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layoutmaster
Joined: 18 Mar 2008
Posts: 182
Helped: 27
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| 14 May 2008 19:15 drc lvs errors |
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Hi vlsi,
The poly end cap is an effect that has to do with the POLY etching process, when the photolitography is being done causes some rounding effect on poly lines so, in small MOS (due to selfalign process) it might be an issue...
Solutions: THere are 2
1- In layout realm... TO make bigger MOS transistors in order to minimize the etching effects.
2 - Outside our spectre... There are some processing techniques to minimize the effect.
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moriar
Joined: 28 Aug 2007
Posts: 21
Helped: 3
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| 15 May 2008 9:05 drc lvs errors |
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OPC the end. 
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