| Author |
Message |
midgariano
Joined: 08 May 2008
Posts: 5
|
 08 May 2008 22:54 Mosfet Mismatch |
|
|
|
Hello Everybody.
I need some imformation about the mismatch of the mosfet transistors, especially about this phenomenon in the differencial pairs. I was seeking this topic but I haven't found any information.
I really need that.
Thank's a lot.
|
|
| Back to top |
|
 |
jecyhale
Joined: 19 Feb 2008
Posts: 432
Helped: 46
Location: China
|
| 09 May 2008 5:39 Re: Mosfet Mismatch |
|
|
|
Firstly, Use large area MOSFET.
Sencondly, divide the MOS into two parts, and cross connect them.
Thirdly, add some dummy MOS around them.
|
|
| Back to top |
|
|
spring1860
Joined: 02 Nov 2007
Posts: 94
Helped: 3
|
| 09 May 2008 6:19 Re: Mosfet Mismatch |
|
|
|
hi
maybe this doc helped you
http://www.edaboard.com/viewtopic.php?p=778720#778720
BR
|
|
| Back to top |
|
|
engrak
Joined: 23 Sep 2006
Posts: 60
|
| 09 May 2008 8:18 Mosfet Mismatch |
|
|
|
| plz read allen hasting book.
|
|
| Back to top |
|
|
lvlei0309
Joined: 29 Apr 2008
Posts: 25
Helped: 2
|
| 09 May 2008 11:19 Re: Mosfet Mismatch |
|
|
|
| mismatch prob, u can consider it on the aspect of offset volt
|
|
| Back to top |
|
|
forkschgrad
Joined: 06 Apr 2007
Posts: 284
Helped: 8
Location: Philippines
|
| 09 May 2008 18:03 Re: Mosfet Mismatch |
|
|
|
| any layout books that will not discuss it is a dump.
|
|
| Back to top |
|
|
dabing
Joined: 14 Dec 2006
Posts: 25
Helped: 3
|
| 10 May 2008 6:29 Re: Mosfet Mismatch |
|
|
|
In my opinion
first, you can use symmetry structure which you can find in many books.
second, you can refer to the foundry which you can get their PCM or electronics parameter, and maybe here are some discreption about mismatch parameter. You can calculate the MOS by the mismatch parameter.
third, you could know the circuit's precision.
|
|
| Back to top |
|
|
tia_design
Joined: 22 Feb 2005
Posts: 101
Helped: 3
|
| 14 May 2008 6:11 Re: Mosfet Mismatch |
|
|
|
There are two ways to reduce the offset.
1. through design. choose device with large width. output stage should be banlance to remove the systematic offset. current source's length should be maximized.
2. Through layout, using centroid and interdigitization
|
|
| Back to top |
|
|
kDaniu
Joined: 18 Jun 2007
Posts: 28
Helped: 9
Location: UA->Korea
|
| 16 May 2008 4:03 Mosfet Mismatch |
|
|
|
tia_design, can you push me to the source where is I can read about centroid and interdigitization in layout ?
thanks, Dan
|
|
| Back to top |
|
|
layoutmaster
Joined: 18 Mar 2008
Posts: 182
Helped: 27
|
| 16 May 2008 13:21 Mosfet Mismatch |
|
|
|
| Read Alan Hasting's "The Art of Analog Layout", Chapter 7 is named Matching of Resistors and Capacitors but inside it mention matching techniques applicable to every component, in particular you'll find good explanations and examples of Interdigitation and CommonCentroid.
|
|
| Back to top |
|
|
chibijia
Joined: 16 Jan 2008
Posts: 19
|
| 16 May 2008 18:19 Mosfet Mismatch |
|
|
|
offset volt
the layut and so on all will result the mismatch!
|
|
| Back to top |
|
|
