Problem with one Verilog statement

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firefoxPL

Joined: 18 Mar 2008
Posts: 40
Helped: 5
Location: Poznan, POLAND

08 May 2008 16:02 Problem with one Verilog statement

Hello, I am currently porting demo from Xilinx for XUPV2P board for controling VDEC from Verilog to VHDL and I have problem with understanding one phrase:

Code:

assign TRS = ((~|YCrCb_rg2[9:2]) & (~|YCrCb_rg3[9:2]) & (&YCrCb_rg4[9:2]));

TRS is a 1-bit signal, I did something like this in VHDL but I am not sure whether it is right:

Code:

TRS <= ((((YCrCb_rg2(9) nor YCrCb_rg2(8)) nor (YCrCb_rg2(7) nor YCrCb_rg2(6))) nor ((YCrCb_rg2(5) nor YCrCb_rg2(4)) nor (YCrCb_rg2(3) nor YCrCb_rg2(2))))
and (((YCrCb_rg3(9) nor YCrCb_rg3(8)) nor (YCrCb_rg3(7) nor YCrCb_rg3(6))) nor ((YCrCb_rg3(5) nor YCrCb_rg3(4)) nor (YCrCb_rg3(3) nor YCrCb_rg3(2)))))
and (((YCrCb_rg2(9) and YCrCb_rg2(8)) and (YCrCb_rg2(7) and YCrCb_rg2(6))) and ((YCrCb_rg2(5) and YCrCb_rg2(4)) and (YCrCb_rg2(3) and YCrCb_rg2(2))));

In fact it is very probable that this is wrong and thats why the project doesn't work Razz

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FvM

Joined: 22 Jan 2008
Posts: 5154
Helped: 767
Location: Bochum, Germany

08 May 2008 19:58 Re: Problem with one Verilog statement

To my opinion, the translation of the Verilog reductional operators expression is correct exept for the nor chaining which creates wrong polarity. Furthermore I would expect a logical and && between the three partial expressions, but the difference shouldn't matter in this place.

Code:

TRS <= not (YCrCb_rg2(9) or YCrCb_rg2(8) or YCrCb_rg2(7) or YCrCb_rg2(6) or YCrCb_rg2(5) or YCrCb_rg2(4) or YCrCb_rg2(3) or YCrCb_rg2(2))
and not(YCrCb_rg3(9) or YCrCb_rg3(8) or YCrCb_rg3(7) or YCrCb_rg3(6) or YCrCb_rg3(5) or YCrCb_rg3(4) or YCrCb_rg3(3) or YCrCb_rg3(2))
and (YCrCb_rg2(9) and YCrCb_rg2(8) and YCrCb_rg2(7) and YCrCb_rg2(6) and YCrCb_rg2(5) and YCrCb_rg2(4) and (YCrCb_rg2(3) and YCrCb_rg2(2));

echo47

Joined: 07 Apr 2002
Posts: 4206
Helped: 566

09 May 2008 14:47 Problem with one Verilog statement

I don't know VHDL, but there's got to be an easier way to write that expression.
The Verilog statement sets TRS to 1 if the following is true:

YCrCb_rg2[9:2] is 00000000
and
YCrCb_rg3[9:2] is 00000000
and
YCrCb_rg4[9:2] is 11111111

firefoxPL

Joined: 18 Mar 2008
Posts: 40
Helped: 5
Location: Poznan, POLAND

09 May 2008 15:38 Re: Problem with one Verilog statement

echo47 wrote:

that should be really helpful thanks a lot

lucbra

Joined: 30 Oct 2003
Posts: 161
Helped: 6
Location: Belgium

10 May 2008 9:42 Re: Problem with one Verilog statement

Maybe something like this:
TRS <= '1' when ((YCrCb_rg2(9 downto 2) = "00000000") and
(YCrCb_rg3(9 downto 2) = "00000000") and
(YCrCb_rg4(9 downto 2) = "11111111"))
else '0';

firefoxPL

Joined: 18 Mar 2008
Posts: 40
Helped: 5
Location: Poznan, POLAND

10 May 2008 9:45 Re: Problem with one Verilog statement

lucbra wrote:

Maybe something like this:
TRS <= '1' when ((YCrCb_rg2(9 downto 2) = "00000000") and
(YCrCb_rg3(9 downto 2) = "00000000") and
(YCrCb_rg4(9 downto 2) = "11111111"))
else '0';

I was thinking exactly the same thing Smile