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balasub
Joined: 15 May 2007 Posts: 32
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27 Mar 2008 18:18 crc |
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hi,
anyone coded ecrc block used in PCIe?
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sree205
Joined: 13 Mar 2006 Posts: 421 Helped: 30
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28 Mar 2008 9:22 crc |
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http://www.easics.com/webtools/crctool
use this website to generate code in either verilog or vhdl to implement crc.
some more posts where crc is discussed
http://www.edaboard.com/viewtopic.php?t=145208&highlight=crc
http://www.edaboard.com/viewtopic.php?t=265738&highlight=crc
http://www.edaboard.com/viewtopic.php?t=119359&highlight=crc
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28 Mar 2008 9:22 Ads |
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balasub
Joined: 15 May 2007 Posts: 32
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31 Mar 2008 14:25 Re: crc |
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hi,
thanks for the pointers...
i did create a crc routine..
now the problem is when i send data padded with the crc the receiver is reporting a crc error.
how do i debug this?
i am kind of stuck...
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FvM
Joined: 22 Jan 2008 Posts: 5154 Helped: 766 Location: Bochum, Germany
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31 Mar 2008 23:27 Re: crc |
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Could it be that the receiver just uses another crc algorithm (different polynomial or additional parameters)?
You have to analyze data with known correct crc to find out the used algorithm. of course it may be also an error in implementation. You can use one of the web crc calculators e. g. linked at wikipedia to check your crc results.
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sree205
Joined: 13 Mar 2006 Posts: 421 Helped: 30
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02 Apr 2008 5:29 crc |
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| Assuming that you have a data width of 32 in the transmitter and another 8 bits of crc bits padded, can you tell me how you are doing the checking on the receiver side?
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balasub
Joined: 15 May 2007 Posts: 32
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02 Apr 2008 7:03 Re: crc |
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hi sree,
here 32 bit crc is used for a data width of 32.
I use a protected code at the receiver side.So i have no visibility.
But this has to comply with the spec hence i guess the problem has to be at my end.
Meaning the way i generate the crc ( i am coding it with respect to the SPEC too).
So just need to debug my code and not sure of a better way to do this.
Added after 46 minutes:
basically i am looking for ecrc/lcrc check for PCIe...
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sree205
Joined: 13 Mar 2006 Posts: 421 Helped: 30
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02 Apr 2008 8:44 Re: crc |
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If you feel that the problem might be at your end, have u checked the parallel crc encoder circuit that you are using with a serial LFSR ? if i'm not mistaken, it'll take the same number of clock cycles as the degree of ur polynomial
if u want to, i can post the serial crc code if u provide the polynomial
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balasub
Joined: 15 May 2007 Posts: 32
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02 Apr 2008 12:16 Re: crc |
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hi,
i use the 32 bit crc whose polynomial is 04c11db7
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sree205
Joined: 13 Mar 2006 Posts: 421 Helped: 30
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02 Apr 2008 14:17 crc |
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module crc (clk,reset,din,checksum);
input clk,reset;
input din;
output [31:0] checksum;
wire [31:0] checksum;
reg [31:0] acc;
always@(posedge clk or negedge reset)
if(!reset)
acc <= 32'b0;
else
begin
acc[0] <= acc[31] ^ din;
acc[1] <= acc[0] ^ acc[31] ^ din;
acc[2] <= acc[1] ^ acc[31] ^ din;
acc[3] <= acc[2];
acc[4] <= acc[3] ^ acc[31] ^ din;
acc[5] <= acc[4] ^ acc[31] ^ din;
acc[6] <= acc[5];
acc[7] <= acc[6] ^ acc[31] ^ din;
acc[8] <= acc[7] ^ acc[31] ^ din;
acc[9] <= acc[8];
acc[10] <= acc[9] ^ acc[31] ^ din;
acc[11] <= acc[10] ^ acc[31] ^ din;
acc[12] <= acc[11] ^ acc[31] ^ din;
acc[13] <= acc[12];
acc[14] <= acc[13];
acc[15] <= acc[14];
acc[16] <= acc[15] ^ acc[31] ^ din;
acc[17] <= acc[16];
acc[18] <= acc[17];
acc[19] <= acc[18];
acc[20] <= acc[19];
acc[21] <= acc[20] ^ acc[31] ^ din;
acc[22] <= acc[21] ^ acc[31] ^ din;
acc[23] <= acc[22];
acc[24] <= acc[23];
acc[25] <= acc[24] ^ acc[31] ^ din;
acc[26] <= acc[25];
acc[27] <= acc[26];
acc[28] <= acc[27];
acc[29] <= acc[28];
acc[30] <= acc[29];
acc[31] <= acc[30];
end
assign checksum = acc;
endmodule
give serial input data and check after 27 clock pulses and let me know if it works.
hope i'm not wrong
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balasub
Joined: 15 May 2007 Posts: 32
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03 Apr 2008 6:50 Re: crc |
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hi sree,
tried this but i am still not sure...just new to design..
can u post ur testbench for this...
thanks!
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OutputLogic
Joined: 11 Jun 2009 Posts: 20 Location: San Jose, CA
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11 Jun 2009 23:44 Re: crc |
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There is an online tool that can generate CRC Verilog or VHDL code. It's on http://outputlogic.com
Hope it helps
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