VLSI Interview Questions

EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital) -> VLSI Interview Questions

Author

Message

satish23

Joined: 14 Mar 2008
Posts: 23

18 Mar 2008 8:24 vlsi interview questions

VLSI

1. Explain why & how a MOSFET works.

2. Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width (c) considering Channel Length Modulation

3. Explain the various MOSFET Capacitances & their significance

4. Draw a CMOS Inverter. Explain its transfer characteristics

5. Explain sizing of the inverter

6. How do you size NMOS and PMOS transistors to increase the threshold voltage?

7. What is Noise Margin? Explain the procedure to determine Noise Margin

8. Give the expression for CMOS switching power dissipation

9. What is Body Effect?

10. Describe the various effects of scaling

11. Give the expression for calculating Delay in CMOS circuit

12. What happens to delay if you increase load capacitance?

13. What happens to delay if we include a resistance at the output of a CMOS
circuit?

14. What are the limitations in increasing the power supply to reduce delay?

15. How does Resistance of the metal lines vary with increasing thickness and increasing length?

16. You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the center metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

17. What happens if we increase the number of contacts or via from one metal layer to the next?

18. Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

19. Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

20. Draw the stick diagram of a NOR gate. Optimize it

21. For CMOS logic, give the various techniques you know to minimize power consumption

22. What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus

23. Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?

24. In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

25. Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

26. Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

27. Why don’t we use just one NMOS or PMOS transistor as a transmission gate?

28. For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

29. Draw a 6-T SRAM Cell and explain the Read and Write operations

30. Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)

31. What happens if we use an Inverter instead of the Differential Sense Amplifier?

32. Draw the SRAM Write Circuitry

33. Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

34. How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM’s performance?

35. What’s the critical path in a SRAM?

36. Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

37. Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers

38. In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

39. How can you model a SRAM at RTL Level?

40. What’s the difference between Testing & Verification?

41. For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

42. What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

www.testbench.in

Joined: 04 Jun 2008
Posts: 46
Helped: 2

07 Jul 2008 12:04 vlsi interview questions with answers

For fronted related interview questions

http://www.testbench.in

.

Google
AdSense
Google Adsense

07 Jul 2008 12:04 Ads

kumarans

Joined: 04 Aug 2007
Posts: 46

29 May 2009 10:06 stick diagram of cmos inverter

Can any one help me in getting the mentor grapics calibre option related questions

samirkag

Joined: 23 Jan 2007
Posts: 7
Helped: 1

31 May 2009 22:20 sram interview questions

Srsly, who asks these kinda qns??

ljxpjpjljx

Joined: 05 May 2008
Posts: 533
Helped: 12
Location: Shang Hai

01 Jun 2009 5:05 vlsi interview question

so mang question, interview is not so easy!

vlsichipdesigner

Joined: 09 May 2007
Posts: 112
Helped: 6

02 Jun 2009 14:14 vlsi verification interview questions

hi,

my 2 cents,

i had coined frequently asked interview questions and the best part is answers are also available , for free, most of the sites would talk about questions and its hard to find answers.

to know the questions and answers visit the website, i had spent lot of my time to help the chip design engineers, hope it is useful...

best regards,
chip design made easy
http://www.vlsichipdesign.com