layoutmaster
Joined: 18 Mar 2008
Posts: 183
Helped: 27
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 11 Apr 2008 18:32 Floor Planning Issues |
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Main concepts:
- Identify noisy and noise sensitive blocks in order to place them as far as possible. ALso, the idea is to join all noisy blocks together.
- BOnd pads placement.
- PWR and GND main lines preliminary path plannification.
- Clock or noisy lines path identification (if possible the idea is to make them as short as possible by placing their generating blocks according this)
- Carefull identification and placement selection of teh component with higher power dissipation, in order to know how thermal gradients will be in your chip.
ANd many many other things, but with this first ones you'll have a more than good starting point for your design...
Hope this helps.
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