Sobakava
Joined: 27 Mar 2002
Posts: 358
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 13 Dec 2002 10:18 FIXED Entry: VERILOG |
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I have problem with following code:
Module has a clock input. It generates some
outputs. For instance, I need a frame pulse
at the output (5 cycle duration) at every
56 cycles of clock. There is a F1 output.
It is High until 30th cycle, then it will
be half of clock.
F2 should be F1&Clock signal.
But there are some unwanted short pulses (X) appear on F2:
............................ a
|11111111|_________|11111111|_____clock
_|111111111111111111|_____________F1
__|11111111|_________|X|__________F2
//I hope this diagram looks fine after submit  //
I think because of the delay clock to F1, F1 and clock
becomes High at (a). (then F2=F1 AND CLOCK becomes high)
I synthesised this to @ltera FLEX EPF10K10 FPGA and I
see the (X) pulse (10ns width and ~1V amplitude) @40Mhz clock
by and oscilloscope. It appears also simulation.
How can I eliminate such unwanted signals in Verilog design?
Regards
module generator(clock,frame,cycle,F1,F2);
input clock;
output F1,F2;
reg F1;
output [12:0] cycle;
reg [12:0] cycle;
output frame;
reg frame;
assign F2=F1&clock;
always @(posedge clock)
begin
cycle=cycle+1;
if (cycle < 30)
F1=1;
else
F1=~F1;
if (cycle == 50)
frame=1;
if (cycle == 55)
frame=0;
if (cycle==56)
cycle=0;
end
endmodule
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radix
Joined: 23 Jul 2002
Posts: 108
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| 13 Dec 2002 17:51 |
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You will definitely get a pulse where you are seeing it. The pulse is going to be proportional to the propagation delay of the register that is capturing F1. The problem is that in the statement:
F2 = F1 and CLK
F1 doesn't change until prop delay time after CLK arrives. So when the output of F1 is supposed to go from high to low, it won't do so until after prop delay time. In the interim, F1 and CLK and high, hence F2 is high. Even though you are simulating with zero delay, the simulator is smart enough to know that there will be some delay through the flop and shows you a glitch.
Radix
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